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yosys/backends/btor
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Ahmed Irfan d3c67ad9b6 Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 
added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc
 		2014-09-22 11:35:04 +02:00
..
Makefile.inc btor 2014-01-03 10:52:44 +01:00
README Added BTOR backend README file 2014-02-05 18:31:10 +01:00
btor.cc Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 2014-09-22 11:35:04 +02:00
btor.ys modified btor synthesis script for correct use of splice command. 2014-02-12 13:38:28 +01:00
verilog2btor.sh Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 2014-09-22 11:35:04 +02:00

README 

This is the Yosys BTOR backend.
It is developed by Ahmed Irfan <irfan@fbk.eu> - Fondazione Bruno Kessler, Trento, Italy

Master git repository for the BTOR backend:
https://github.com/ahmedirfan1983/yosys/tree/btor


[[CITE]] BTOR: Bit-Precise Modelling of Word-Level Problems for Model Checking 
Johannes Kepler University, Linz, Austria
http://fmv.jku.at/papers/BrummayerBiereLonsing-BPR08.pdf


Todos:
------

- Add checks for unsupported stuff
    - unsupported cell types
    - async resets
    - etc..

- Add support for $pmux and $lut cells