mirror of https://github.com/YosysHQ/yosys.git
93 lines
1.5 KiB
Systemverilog
93 lines
1.5 KiB
Systemverilog
module top;
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function automatic [31:0] operation1;
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input [4:0] rounds;
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input integer num;
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integer i;
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begin
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begin : shadow
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integer rounds;
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rounds = 0;
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end
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for (i = 0; i < rounds; i = i + 1)
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num = num * 2;
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operation1 = num;
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end
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endfunction
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function automatic [31:0] pass_through;
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input [31:0] inp;
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pass_through = inp;
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endfunction
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function automatic [31:0] operation2;
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input [4:0] inp;
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input integer num;
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begin
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inp[0] = inp[0] ^ 1;
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operation2 = num * inp;
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end
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endfunction
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function automatic [31:0] operation3;
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input [4:0] rounds;
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input integer num;
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reg [4:0] rounds;
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integer i;
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begin
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begin : shadow
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integer rounds;
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rounds = 0;
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end
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for (i = 0; i < rounds; i = i + 1)
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num = num * 2;
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operation3 = num;
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end
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endfunction
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function automatic [16:0] operation4;
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input [15:0] a;
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input b;
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operation4 = {a, b};
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endfunction
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function automatic integer operation5;
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input x;
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integer x;
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operation5 = x;
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endfunction
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wire [31:0] a;
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assign a = 2;
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parameter A = 3;
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wire [31:0] x1;
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assign x1 = operation1(A, a);
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wire [31:0] x1b;
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assign x1b = operation1(pass_through(A), a);
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wire [31:0] x2;
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assign x2 = operation2(A, a);
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wire [31:0] x3;
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assign x3 = operation3(A, a);
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wire [16:0] x4;
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assign x4 = operation4(a[15:0], 0);
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wire [31:0] x5;
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assign x5 = operation5(64);
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always_comb begin
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assert(a == 2);
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assert(A == 3);
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assert(x1 == 16);
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assert(x1b == 16);
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assert(x2 == 4);
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assert(x3 == 16);
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assert(x4 == a << 1);
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assert(x5 == 64);
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end
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endmodule
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