mirror of https://github.com/YosysHQ/yosys.git
61 lines
1.0 KiB
Verilog
61 lines
1.0 KiB
Verilog
module testbench ();
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reg clk = 0;
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reg rst = 1;
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reg req3 = 0;
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reg req2 = 0;
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reg req1 = 0;
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reg req0 = 0;
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wire gnt3;
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wire gnt2;
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wire gnt1;
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wire gnt0;
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// Clock generator
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always #1 clk = ~clk;
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integer file;
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always @(posedge clk)
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$fdisplay(file, "%b", {gnt3, gnt2, gnt1, gnt0});
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initial begin
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file = $fopen(`outfile);
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repeat (5) @ (posedge clk);
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rst <= 0;
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repeat (1) @ (posedge clk);
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req0 <= 1;
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repeat (1) @ (posedge clk);
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req0 <= 0;
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repeat (1) @ (posedge clk);
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req0 <= 1;
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req1 <= 1;
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repeat (1) @ (posedge clk);
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req2 <= 1;
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req1 <= 0;
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repeat (1) @ (posedge clk);
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req3 <= 1;
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req2 <= 0;
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repeat (1) @ (posedge clk);
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req3 <= 0;
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repeat (1) @ (posedge clk);
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req0 <= 0;
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repeat (1) @ (posedge clk);
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#10 $finish;
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end
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// Connect the DUT
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arbiter U (
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clk,
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rst,
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req3,
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req2,
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req1,
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req0,
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gnt3,
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gnt2,
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gnt1,
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gnt0
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);
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endmodule
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