Clifford Wolf e807e88b60 Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2019-04-23 21:36:59 +02:00
..
achronix	Reduce amount of trailing whitespace in code base	2019-02-28 14:58:11 -08:00
anlogic	Reduce amount of trailing whitespace in code base	2019-02-28 14:58:11 -08:00
common	Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature	2019-04-23 21:36:59 +02:00
coolrunner2	Unify usage of noflatten among architectures	2019-01-04 11:37:25 +01:00
easic	Fix typographical and grammatical errors and inconsistencies.	2019-01-02 13:12:17 +00:00
ecp5	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
gowin	Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master	2019-04-22 09:09:27 +02:00
greenpak4	techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module	2019-02-26 09:40:46 -08:00
ice40	ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments	2019-04-21 21:40:11 +01:00
intel	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
sf2	Add link to SF2 / igloo2 macro library guide	2019-03-07 09:08:26 -08:00
xilinx	Update help message	2019-04-22 11:38:23 -07:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00