mirror of https://github.com/YosysHQ/yosys.git
32 lines
813 B
Verilog
32 lines
813 B
Verilog
//-----------------------------------------------------
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// Design Name : one_hot_cnt
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// File Name : one_hot_cnt.v
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// Function : 8 bit one hot counter
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module one_hot_cnt (
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out , // Output of the counter
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enable , // enable for counter
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clk , // clock input
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reset // reset input
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);
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//----------Output Ports--------------
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output [7:0] out;
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//------------Input Ports--------------
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input enable, clk, reset;
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//------------Internal Variables--------
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reg [7:0] out;
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//-------------Code Starts Here-------
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always @ (posedge clk)
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if (reset) begin
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out <= 8'b0000_0001 ;
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end else if (enable) begin
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out <= {out[6],out[5],out[4],out[3],
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out[2],out[1],out[0],out[7]};
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end
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endmodule
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