mirror of https://github.com/YosysHQ/yosys.git
70 lines
1.0 KiB
Verilog
70 lines
1.0 KiB
Verilog
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// `define ASYNC_RESET
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module test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b);
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input clk, reset, button_a, button_b;
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output reg red_a, green_a, red_b, green_b;
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(* gentb_constant = 0 *)
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wire reset;
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integer state;
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reg [3:0] cnt;
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`ifdef ASYNC_RESET
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always @(posedge clk, posedge reset)
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`else
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always @(posedge clk)
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`endif
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begin
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cnt <= 0;
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red_a <= 1;
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red_b <= 1;
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green_a <= 0;
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green_b <= 0;
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if (reset)
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state <= 100;
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else
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case (state)
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100: begin
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if (button_a && !button_b)
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state <= 200;
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if (!button_a && button_b)
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state <= 300;
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end
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200: begin
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red_a <= 0;
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green_a <= 1;
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cnt <= cnt + 1;
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if (cnt == 5)
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state <= 210;
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end
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210: begin
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red_a <= 0;
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green_a <= cnt[0];
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cnt <= cnt + 1;
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if (cnt == 10)
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state <= 100;
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end
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300: begin
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red_b <= 0;
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green_b <= 1;
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cnt <= cnt + 1;
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if (cnt == 5)
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state <= 310;
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end
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310: begin
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red_b <= 0;
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green_b <= cnt[0];
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cnt <= cnt + 1;
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if (cnt == 10)
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state <= 100;
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end
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endcase
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end
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endmodule
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