yosys/tests/hana/test_simulation_mux_4_test.v

11 lines
212 B
Verilog

module test(input [3:0] in, input [1:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule