mirror of https://github.com/YosysHQ/yosys.git
30 lines
507 B
Verilog
30 lines
507 B
Verilog
module test(out, i0, i1, i2, i3, s1, s0);
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output out;
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input i0, i1, i2, i3;
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input s1, s0;
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assign out = (~s1 & s0 & i0) |
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(~s1 & s0 & i1) |
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(s1 & ~s0 & i2) |
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(s1 & s0 & i3);
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endmodule
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module ternaryop(out, i0, i1, i2, i3, s1, s0);
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output out;
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input i0, i1, i2, i3;
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input s1, s0;
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assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0);
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endmodule
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module fulladd4(sum, c_out, a, b, c_in);
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output [3:0] sum;
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output c_out;
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input [3:0] a, b;
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input c_in;
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assign {c_out, sum} = a + b + c_in;
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endmodule
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