mirror of https://github.com/YosysHQ/yosys.git
27 lines
601 B
Verilog
27 lines
601 B
Verilog
module demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);
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output out0, out1, out2, out3;
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reg out0, out1, out2, out3;
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input in;
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input s1, s0;
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reg [3:0] encoding;
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reg [1:0] state;
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always @(encoding) begin
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case (encoding)
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4'bxx11: state = 1;
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4'bx0xx: state = 3;
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4'b11xx: state = 4;
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4'bx1xx: state = 2;
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4'bxx1x: state = 1;
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4'bxxx1: state = 0;
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default: state = 0;
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endcase
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end
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always @(encoding) begin
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case (encoding)
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4'b0000: state = 1;
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default: state = 0;
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endcase
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end
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endmodule
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