mirror of https://github.com/YosysHQ/yosys.git
15 lines
383 B
Verilog
15 lines
383 B
Verilog
module test(input [31:0] a, b, c, output [31:0] x, y, z);
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unit_x unit_x_inst (.a(a), .b(b), .c(c), .x(x));
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unit_y unit_y_inst (.a(a), .b(b), .c(c), .y(y));
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assign z = a ^ b ^ c;
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endmodule
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module unit_x(input [31:0] a, b, c, output [31:0] x);
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assign x = (a & b) | c;
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endmodule
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module unit_y(input [31:0] a, b, c, output [31:0] y);
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assign y = a & (b | c);
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endmodule
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