riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/tests/errors/syntax_err03.v

8 lines
55 B
Verilog
Raw Blame History

module a;
task to (
input [3]x
);
endtask
endmodule
Reference in New Issue View Git Blame Copy Permalink