This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
6240aec433
yosys
/
backends
/
verilog
History
Martin Povišer
e7b21d2706
write_verilog: Use assign for `$buf`
2024-12-05 18:28:23 +01:00
..
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
verilog_backend.cc
write_verilog: Use assign for `$buf`
2024-12-05 18:28:23 +01:00