yosys/techlibs/quicklogic
Emil J 9f7040b3d1
Merge pull request #4683 from keszybz/use-SOURCE_DATE_EPOCH
Respect $SOURCE_DATE_EPOCH in generate_bram_types_sim.py
2025-01-10 23:43:26 +01:00
..
common synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
pp3 synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
qlf_k6n10f Drop timestamp in generate_bram_types_sim.py 2024-10-30 08:47:18 +01:00
.gitignore add dsp inference 2023-12-04 15:52:02 +01:00
Makefile.inc Fix out of tree build 2023-12-06 09:56:35 +01:00
ql_bram_merge.cc Fix Windows build by forcing initialization order, fixes #4068 2024-01-02 11:26:48 +01:00
ql_bram_types.cc add dsp inference 2023-12-04 15:52:02 +01:00
ql_dsp_io_regs.cc Fix Windows build by forcing initialization order, fixes #4068 2024-01-02 11:26:48 +01:00
ql_dsp_macc.cc Fix out of tree build 2023-12-06 09:11:51 +01:00
ql_dsp_macc.pmg ql_dsp_macc: Tune DSP inference code 2023-12-04 15:52:02 +01:00
ql_dsp_simd.cc hashlib: hash_eat -> hash_into 2024-12-18 15:09:25 +01:00
synth_quicklogic.cc quicklogic: Avoid carry chains in division mapping 2024-09-19 12:18:47 +02:00