mirror of https://github.com/YosysHQ/yosys.git
20 lines
389 B
Verilog
20 lines
389 B
Verilog
// Demo for memory initialization
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module demo7;
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wire [2:0] addr = $anyseq;
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reg [15:0] memory [0:7];
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initial begin
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memory[0] = 1331;
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memory[1] = 1331 + 1;
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memory[2] = 1331 + 2;
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memory[3] = 1331 + 4;
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memory[4] = 1331 + 8;
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memory[5] = 1331 + 16;
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memory[6] = 1331 + 32;
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memory[7] = 1331 + 64;
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end
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assert property (1000 < memory[addr] && memory[addr] < 2000);
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endmodule
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