This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
60611b936b
yosys
/
tests
/
errors
/
syntax_err10.v
4 lines
48 B
Verilog
Raw
Blame
History
module
a
;
parameter
integer
[
2
:
0
]
x
=
0
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink