mirror of https://github.com/YosysHQ/yosys.git
25 lines
520 B
Verilog
25 lines
520 B
Verilog
module v2k_reg();
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// v2k allows to init variables
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reg a = 0;
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// Here only last variable is set to 0, i.e d = 0
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// Rest b, c are set to x
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reg b, c, d = 0;
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// reg data type can be signed in v2k
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// We can assign with signed constants
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reg signed [7:0] data = 8'shF0;
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// Function can return signed values
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// Its ports can contain signed ports
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function signed [7:0] adder;
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input a_in;
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input b_in;
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input c_in;
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input signed [7:0] data_in;
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begin
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adder = a_in + b_in + c_in + data_in;
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end
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endfunction
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endmodule
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