mirror of https://github.com/YosysHQ/yosys.git
275 lines
9.6 KiB
C++
275 lines
9.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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#include "kernel/ff.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Clk2fflogicPass : public Pass {
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Clk2fflogicPass() : Pass("clk2fflogic", "convert clocked FFs to generic $ff cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" clk2fflogic [options] [selection]\n");
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log("\n");
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log("This command replaces clocked flip-flops with generic $ff cells that use the\n");
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log("implicit global clock. This is useful for formal verification of designs with\n");
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log("multiple clocks.\n");
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log("\n");
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}
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SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity, bool is_fine, IdString past_sig_id) {
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if (!is_fine)
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return wrap_async_control(module, sig, polarity, past_sig_id);
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return wrap_async_control_gate(module, sig, polarity, past_sig_id);
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}
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SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity, IdString past_sig_id) {
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Wire *past_sig = module->addWire(past_sig_id, GetSize(sig));
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past_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S0 : State::S1, GetSize(sig));
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module->addFf(NEW_ID, sig, past_sig);
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if (polarity)
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sig = module->Or(NEW_ID, sig, past_sig);
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else
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sig = module->And(NEW_ID, sig, past_sig);
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if (polarity)
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return sig;
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else
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return module->Not(NEW_ID, sig);
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}
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SigSpec wrap_async_control_gate(Module *module, SigSpec sig, bool polarity, IdString past_sig_id) {
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Wire *past_sig = module->addWire(past_sig_id);
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past_sig->attributes[ID::init] = polarity ? State::S0 : State::S1;
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module->addFfGate(NEW_ID, sig, past_sig);
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if (polarity)
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sig = module->OrGate(NEW_ID, sig, past_sig);
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else
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sig = module->AndGate(NEW_ID, sig, past_sig);
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if (polarity)
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return sig;
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else
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return module->NotGate(NEW_ID, sig);
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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// bool flag_noinit = false;
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log_header(design, "Executing CLK2FFLOGIC pass (convert clocked FFs to generic $ff cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-noinit") {
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// flag_noinit = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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FfInitVals initvals(&sigmap, module);
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for (auto &mem : Mem::get_selected_memories(module))
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{
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for (int i = 0; i < GetSize(mem.rd_ports); i++) {
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auto &port = mem.rd_ports[i];
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if (port.clk_enable)
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log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
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"Call \"memory\" with -nordff to avoid this error.\n", i, log_id(mem.memid), log_id(module));
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}
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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{
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auto &port = mem.wr_ports[i];
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if (!port.clk_enable)
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continue;
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log("Modifying write port %d on memory %s.%s: CLK=%s, A=%s, D=%s\n",
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i, log_id(module), log_id(mem.memid), log_signal(port.clk),
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log_signal(port.addr), log_signal(port.data));
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Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", log_id(mem.memid), i, log_signal(port.clk))));
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past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0;
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module->addFf(NEW_ID, port.clk, past_clk);
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SigSpec clock_edge_pattern;
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if (port.clk_polarity) {
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clock_edge_pattern.append(State::S0);
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clock_edge_pattern.append(State::S1);
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} else {
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clock_edge_pattern.append(State::S1);
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clock_edge_pattern.append(State::S0);
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}
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SigSpec clock_edge = module->Eqx(NEW_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern);
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SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", log_id(mem.memid), i)), GetSize(port.en));
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module->addFf(NEW_ID, port.en, en_q);
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SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", log_id(mem.memid), i)), GetSize(port.addr));
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module->addFf(NEW_ID, port.addr, addr_q);
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SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", log_id(mem.memid), i)), GetSize(port.data));
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module->addFf(NEW_ID, port.data, data_q);
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port.clk = State::S0;
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port.en = module->Mux(NEW_ID, Const(0, GetSize(en_q)), en_q, clock_edge);
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port.addr = addr_q;
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port.data = data_q;
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port.clk_enable = false;
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port.clk_polarity = false;
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}
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mem.emit();
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}
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for (auto cell : vector<Cell*>(module->selected_cells()))
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{
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SigSpec qval;
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if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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FfData ff(&initvals, cell);
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if (ff.has_gclk) {
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// Already a $ff or $_FF_ cell.
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continue;
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}
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if (ff.has_clk) {
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log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
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} else if (ff.has_aload) {
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log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
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} else {
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// $sr.
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log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
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}
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ff.remove();
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// Strip spaces from signal name, since Yosys IDs can't contain spaces
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// Spaces only occur when we have a signal that's a slice of a larger bus,
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// e.g. "\myreg [5:0]", so removing spaces shouldn't result in loss of uniqueness
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std::string sig_q_str = log_signal(ff.sig_q);
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sig_q_str.erase(std::remove(sig_q_str.begin(), sig_q_str.end(), ' '), sig_q_str.end());
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Wire *past_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#past_q_wire", sig_q_str.c_str())), ff.width);
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if (!ff.is_fine) {
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module->addFf(NEW_ID, ff.sig_q, past_q);
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} else {
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module->addFfGate(NEW_ID, ff.sig_q, past_q);
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}
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if (!ff.val_init.is_fully_undef())
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initvals.set_init(past_q, ff.val_init);
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if (ff.has_clk) {
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ff.unmap_ce_srst();
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Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#past_clk#%s", sig_q_str.c_str(), log_signal(ff.sig_clk))));
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initvals.set_init(past_clk, ff.pol_clk ? State::S1 : State::S0);
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if (!ff.is_fine)
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module->addFf(NEW_ID, ff.sig_clk, past_clk);
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else
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module->addFfGate(NEW_ID, ff.sig_clk, past_clk);
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SigSpec clock_edge_pattern;
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if (ff.pol_clk) {
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clock_edge_pattern.append(State::S0);
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clock_edge_pattern.append(State::S1);
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} else {
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clock_edge_pattern.append(State::S1);
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clock_edge_pattern.append(State::S0);
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}
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SigSpec clock_edge = module->Eqx(NEW_ID, {ff.sig_clk, SigSpec(past_clk)}, clock_edge_pattern);
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Wire *past_d = module->addWire(NEW_ID_SUFFIX(stringf("%s#past_d_wire", sig_q_str.c_str())), ff.width);
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if (!ff.is_fine)
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module->addFf(NEW_ID, ff.sig_d, past_d);
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else
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module->addFfGate(NEW_ID, ff.sig_d, past_d);
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if (!ff.val_init.is_fully_undef())
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initvals.set_init(past_d, ff.val_init);
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if (!ff.is_fine)
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qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
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else
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qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
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} else {
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qval = past_q;
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}
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if (ff.has_aload) {
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SigSpec sig_aload = wrap_async_control(module, ff.sig_aload, ff.pol_aload, ff.is_fine, NEW_ID);
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if (!ff.is_fine)
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qval = module->Mux(NEW_ID, qval, ff.sig_ad, sig_aload);
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else
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qval = module->MuxGate(NEW_ID, qval, ff.sig_ad, sig_aload);
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}
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if (ff.has_sr) {
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SigSpec setval = wrap_async_control(module, ff.sig_set, ff.pol_set, ff.is_fine, NEW_ID);
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SigSpec clrval = wrap_async_control(module, ff.sig_clr, ff.pol_clr, ff.is_fine, NEW_ID);
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if (!ff.is_fine) {
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clrval = module->Not(NEW_ID, clrval);
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qval = module->Or(NEW_ID, qval, setval);
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module->addAnd(NEW_ID, qval, clrval, ff.sig_q);
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} else {
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clrval = module->NotGate(NEW_ID, clrval);
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qval = module->OrGate(NEW_ID, qval, setval);
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module->addAndGate(NEW_ID, qval, clrval, ff.sig_q);
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}
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} else if (ff.has_arst) {
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IdString id = NEW_ID_SUFFIX(stringf("%s#past_arst#%s", sig_q_str.c_str(), log_signal(ff.sig_arst)));
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SigSpec arst = wrap_async_control(module, ff.sig_arst, ff.pol_arst, ff.is_fine, id);
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if (!ff.is_fine)
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module->addMux(NEW_ID, qval, ff.val_arst, arst, ff.sig_q);
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else
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module->addMuxGate(NEW_ID, qval, ff.val_arst[0], arst, ff.sig_q);
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} else {
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module->connect(ff.sig_q, qval);
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}
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}
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}
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}
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}
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} Clk2fflogicPass;
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PRIVATE_NAMESPACE_END
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