mirror of https://github.com/YosysHQ/yosys.git
19 lines
600 B
Plaintext
19 lines
600 B
Plaintext
verific -vlog2k ../yosys-bigsim/softusb_navre/rtl/softusb_navre.v
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verific -import softusb_navre
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memory softusb_navre
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flatten softusb_navre
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rename softusb_navre gate
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read_verilog ../yosys-bigsim/softusb_navre/rtl/softusb_navre.v
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cd softusb_navre; proc; opt; memory; opt; cd ..
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rename softusb_navre gold
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expose -dff -shared gold gate
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miter -equiv -ignore_gold_x -make_assert -make_outputs -make_outcmp gold gate miter
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cd miter
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flatten; opt -undriven
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sat -verify -maxsteps 5 -set-init-undef -set-def-inputs -prove-asserts -tempinduct-def \
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-seq 1 -set-at 1 in_rst 1 # -show-inputs -show-outputs
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