mirror of https://github.com/YosysHQ/yosys.git
72 lines
1.3 KiB
Plaintext
72 lines
1.3 KiB
Plaintext
pattern xilinx_dsp
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state <SigBit> clock
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state <SigSpec> sigA sigB sigY sigS
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state <Cell*> addAB muxAB
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match mul
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select mul->type.in($__MUL25X18)
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endmatch
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match ffA
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select ffA->type.in($dff) /* TODO: $dffe */
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// select nusers(port(ffA, \Q)) == 2
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index <SigSpec> port(ffA, \Q) === port(mul, \A)
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// DSP48E1 does not support clock inversion
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index <SigBit> port(ffA, \CLK_POLARITY) === State::S1
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optional
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endmatch
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code sigA clock
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sigA = port(mul, \A);
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if (ffA) {
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sigA = port(ffA, \D);
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clock = port(ffA, \CLK).as_bit();
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}
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endcode
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match ffB
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select ffB->type.in($dff)
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// select nusers(port(ffB, \Q)) == 2
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index <SigSpec> port(ffB, \Q) === port(mul, \B)
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index <SigBit> port(ffB, \CLK_POLARITY) === State::S1
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optional
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endmatch
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code sigB clock
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sigB = port(mul, \B);
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if (ffB) {
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sigB = port(ffB, \D);
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SigBit c = port(ffB, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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}
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endcode
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match ffY
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select ffY->type.in($dff)
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select nusers(port(ffY, \D)) == 2
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index <SigSpec> port(ffY, \D) === port(mul, \Y)
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index <SigBit> port(ffY, \CLK_POLARITY) === State::S1
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optional
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endmatch
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code sigY clock
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sigY = port(mul, \Y);
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if (ffY) {
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sigY = port(ffY, \Q);
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SigBit c = port(ffY, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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}
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endcode
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