This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
5dffdd229c
yosys
/
tests
/
sim
/
simple_assign.v
9 lines
98 B
Verilog
Raw
Blame
History
module
simple_assign
(
input
wire
in
,
output
wire
out
)
;
assign
out
=
in
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink