mirror of https://github.com/YosysHQ/yosys.git
19 lines
632 B
Verilog
19 lines
632 B
Verilog
// This file exists to map purely-synchronous flops to ABC9 flops, while
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// mapping flops with asynchronous-clear as boxes, this is because ABC9
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// doesn't support asynchronous-clear flops in sequential synthesis.
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module MISTRAL_FF(
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input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA,
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output reg Q
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);
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parameter _TECHMAP_CONSTMSK_ACLR_ = 1'b0;
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// If the async-clear is constant, we assume it's disabled.
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if (_TECHMAP_CONSTMSK_ACLR_ != 1'b0)
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$__MISTRAL_FF_SYNCONLY _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q));
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else
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wire _TECHMAP_FAIL_ = 1;
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endmodule
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