mirror of https://github.com/YosysHQ/yosys.git
35 lines
880 B
Plaintext
35 lines
880 B
Plaintext
read_verilog ../common/latches.v
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design -save read
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hierarchy -top latchp
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_ecp5
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cd latchp # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT4
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select -assert-none t:LUT4 %% t:* %D
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design -load read
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hierarchy -top latchn
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_ecp5
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cd latchn # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT4
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select -assert-none t:LUT4 %% t:* %D
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design -load read
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hierarchy -top latchsr
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_ecp5
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cd latchsr # Constrain all select calls below inside the top module
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select -assert-count 2 t:LUT4
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select -assert-count 1 t:PFUMX
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select -assert-none t:LUT4 t:PFUMX %% t:* %D
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