mirror of https://github.com/YosysHQ/yosys.git
117 lines
3.0 KiB
C
117 lines
3.0 KiB
C
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef COST_H
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#define COST_H
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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struct CellCosts
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{
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static const dict<RTLIL::IdString, int>& default_gate_cost() {
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static const dict<RTLIL::IdString, int> db = {
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{ ID($_BUF_), 1 },
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{ ID($_NOT_), 2 },
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{ ID($_AND_), 4 },
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{ ID($_NAND_), 4 },
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{ ID($_OR_), 4 },
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{ ID($_NOR_), 4 },
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{ ID($_ANDNOT_), 4 },
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{ ID($_ORNOT_), 4 },
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{ ID($_XOR_), 5 },
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{ ID($_XNOR_), 5 },
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{ ID($_AOI3_), 6 },
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{ ID($_OAI3_), 6 },
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{ ID($_AOI4_), 7 },
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{ ID($_OAI4_), 7 },
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{ ID($_MUX_), 4 },
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{ ID($_NMUX_), 4 }
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};
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return db;
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}
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static const dict<RTLIL::IdString, int>& cmos_gate_cost() {
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static const dict<RTLIL::IdString, int> db = {
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{ ID($_BUF_), 1 },
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{ ID($_NOT_), 2 },
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{ ID($_AND_), 6 },
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{ ID($_NAND_), 4 },
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{ ID($_OR_), 6 },
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{ ID($_NOR_), 4 },
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{ ID($_ANDNOT_), 6 },
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{ ID($_ORNOT_), 6 },
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{ ID($_XOR_), 12 },
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{ ID($_XNOR_), 12 },
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{ ID($_AOI3_), 6 },
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{ ID($_OAI3_), 6 },
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{ ID($_AOI4_), 8 },
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{ ID($_OAI4_), 8 },
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{ ID($_MUX_), 12 },
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{ ID($_NMUX_), 10 }
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};
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return db;
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}
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dict<RTLIL::IdString, int> mod_cost_cache;
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const dict<RTLIL::IdString, int> *gate_cost = nullptr;
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Design *design = nullptr;
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int get(RTLIL::IdString type) const
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{
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if (gate_cost && gate_cost->count(type))
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return gate_cost->at(type);
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log_warning("Can't determine cost of %s cell.\n", log_id(type));
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return 1;
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}
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int get(RTLIL::Cell *cell)
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{
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if (gate_cost && gate_cost->count(cell->type))
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return gate_cost->at(cell->type);
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if (design && design->module(cell->type) && cell->parameters.empty())
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{
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RTLIL::Module *mod = design->module(cell->type);
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if (mod->attributes.count(ID(cost)))
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return mod->attributes.at(ID(cost)).as_int();
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if (mod_cost_cache.count(mod->name))
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return mod_cost_cache.at(mod->name);
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int module_cost = 1;
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for (auto c : mod->cells())
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module_cost += get(c);
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mod_cost_cache[mod->name] = module_cost;
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return module_cost;
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}
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log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
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return 1;
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}
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};
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YOSYS_NAMESPACE_END
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#endif
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