mirror of https://github.com/YosysHQ/yosys.git
34 lines
796 B
Verilog
34 lines
796 B
Verilog
// borrowed with some modifications from
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// http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html
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module up3down5(clock, data_in, up, down, carry_out, borrow_out, count_out, parity_out);
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input [8:0] data_in;
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input clock, up, down;
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output reg [8:0] count_out;
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output reg carry_out, borrow_out, parity_out;
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reg [9:0] cnt_up, cnt_dn;
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reg [8:0] count_nxt;
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always @(posedge clock)
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begin
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cnt_dn = count_out - 3'b 101;
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cnt_up = count_out + 2'b 11;
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case ({up,down})
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2'b 00 : count_nxt = data_in;
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2'b 01 : count_nxt = cnt_dn;
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2'b 10 : count_nxt = cnt_up;
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2'b 11 : count_nxt = count_out;
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default : count_nxt = 9'bX;
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endcase
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parity_out <= ^count_nxt;
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carry_out <= up & cnt_up[9];
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borrow_out <= down & cnt_dn[9];
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count_out <= count_nxt;
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end
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endmodule
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