Eddie Hung 5bcde7ccc3 Merge pull request #2045 from YosysHQ/eddie/fix2042 ... verilog: error if no direction given for task arguments, default to input in SV mode		2020-05-14 09:45:54 -07:00
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aiger	aiger: fixes for ports that have start_offset != 0	2020-05-02 10:00:32 -07:00
ast	Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto	2020-05-14 18:06:18 +02:00
blif	kernel: big fat patch to use more ID::*, otherwise ID(*)	2020-04-02 09:51:32 -07:00
ilang	frontend: cleanup to use more ID::*, more dict<> instead of map<>	2020-05-04 10:48:37 -07:00
json	Update JSON front-end to process new attr/param encoding	2019-08-01 12:48:22 +02:00
liberty	kernel: big fat patch to use more ID::*, otherwise ID(*)	2020-04-02 09:51:32 -07:00
rpc	Add WASI platform support.	2020-04-30 18:56:25 +00:00
verific	Add support for non-power-of-two mem chunks in verific importer	2020-05-14 14:38:13 +02:00
verilog	verilog: default to input in sv mode if task/func has no dir ...	2020-05-13 13:33:37 -07:00