mirror of https://github.com/YosysHQ/yosys.git
223 lines
6.1 KiB
Verilog
223 lines
6.1 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// PCM IO Slave Module ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/ss_pcm/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: pcm_slv_top.v,v 1.2 2002/09/17 15:32:50 rudi Exp $
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//
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// $Date: 2002/09/17 15:32:50 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: pcm_slv_top.v,v $
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// Revision 1.2 2002/09/17 15:32:50 rudi
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// *** empty log message ***
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//
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// Revision 1.1.1.1 2002/09/17 15:17:25 rudi
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// Initial Checkin
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//
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//
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//
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//
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//
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//
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//
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//
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`include "timescale.v"
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/*
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PCM Interface
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===============================
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PCM_CLK
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PCM_SYNC
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PCM_DIN
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PCM_DOUT
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*/
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module pcm_slv_top( clk, rst,
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ssel,
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// PCM
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pcm_clk_i, pcm_sync_i, pcm_din_i, pcm_dout_o,
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// Internal Interface
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din_i, dout_o, re_i, we_i);
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input clk, rst;
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input [2:0] ssel; // Number of bits to delay (0-7)
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input pcm_clk_i, pcm_sync_i, pcm_din_i;
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output pcm_dout_o;
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input [7:0] din_i;
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output [7:0] dout_o;
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input re_i;
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input [1:0] we_i;
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///////////////////////////////////////////////////////////////////
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//
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// Local Wires and Registers
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//
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reg pclk_t, pclk_s, pclk_r;
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wire pclk_ris, pclk_fal;
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reg psync;
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reg pcm_sync_r1, pcm_sync_r2, pcm_sync_r3;
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reg tx_go;
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wire tx_data_le;
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reg [15:0] tx_hold_reg;
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reg [7:0] tx_hold_byte_h, tx_hold_byte_l;
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reg [3:0] tx_cnt;
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wire tx_done;
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reg [15:0] rx_hold_reg, rx_reg;
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wire rx_data_le;
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reg rxd_t, rxd;
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reg tx_go_r1, tx_go_r2;
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reg [7:0] psa;
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///////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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always @(posedge clk)
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pclk_t <= #1 pcm_clk_i;
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always @(posedge clk)
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pclk_s <= #1 pclk_t;
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always @(posedge clk)
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pclk_r <= #1 pclk_s;
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assign pclk_ris = !pclk_r & pclk_s;
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assign pclk_fal = pclk_r & !pclk_s;
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///////////////////////////////////////////////////////////////////
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//
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// Retrieve Sync Signal
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//
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always @(posedge clk) // Latch it at falling edge
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if(pclk_fal) pcm_sync_r1 <= #1 pcm_sync_i;
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always @(posedge clk) // resync to rising edge
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if(pclk_ris) psa <= #1 {psa[6:0], pcm_sync_r1};
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always @(posedge clk) //delay bit N
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pcm_sync_r2 <= #1 psa[ssel];
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always @(posedge clk) // edge detector
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pcm_sync_r3 <= #1 pcm_sync_r2;
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always @(posedge clk)
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psync <= #1 !pcm_sync_r3 & pcm_sync_r2;
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///////////////////////////////////////////////////////////////////
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//
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// Transmit Logic
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//
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assign tx_data_le = tx_go & pclk_ris;
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always @(posedge clk)
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if(we_i[1]) tx_hold_byte_h <= #1 din_i;
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always @(posedge clk)
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if(we_i[0]) tx_hold_byte_l <= #1 din_i;
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always @(posedge clk)
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if(!rst) tx_go <= #1 1'b0;
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else
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if(psync) tx_go <= #1 1'b1;
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else
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if(tx_done) tx_go <= #1 1'b0;
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always @(posedge clk)
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if(!rst) tx_hold_reg <= #1 16'h0;
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else
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if(psync) tx_hold_reg <= #1 {tx_hold_byte_h, tx_hold_byte_l};
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else
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if(tx_data_le) tx_hold_reg <= #1 {tx_hold_reg[14:0],1'b0};
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assign pcm_dout_o = tx_hold_reg[15];
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always @(posedge clk)
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if(!rst) tx_cnt <= #1 4'h0;
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else
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if(tx_data_le) tx_cnt <= tx_cnt + 4'h1;
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assign tx_done = (tx_cnt == 4'hf) & tx_data_le;
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///////////////////////////////////////////////////////////////////
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//
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// Recieve Logic
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//
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always @(posedge clk)
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if(pclk_ris) tx_go_r1 <= #1 tx_go;
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always @(posedge clk)
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if(pclk_ris) tx_go_r2 <= #1 tx_go_r1;
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// Receive is in sync with transmit ...
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always @(posedge clk)
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if(pclk_fal) rxd_t <= #1 pcm_din_i;
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always @(posedge clk)
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rxd <= #1 rxd_t;
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assign rx_data_le = (tx_go_r1 | tx_go) & pclk_fal;
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always @(posedge clk)
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if(!rst) rx_hold_reg <= #1 16'h0;
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else
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if(rx_data_le) rx_hold_reg <= #1 {rx_hold_reg[14:0], rxd};
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always @(posedge clk)
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if(!rst) rx_reg <= #1 16'h0;
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else
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if(tx_go_r1 & !tx_go & pclk_ris) rx_reg <= #1 rx_hold_reg;
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assign dout_o = re_i ? rx_reg[15:8] : rx_reg[7:0];
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endmodule
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