mirror of https://github.com/YosysHQ/yosys.git
104 lines
3.3 KiB
Verilog
104 lines
3.3 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Primitives ////
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//// FPU Primitives ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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////////////////////////////////////////////////////////////////////////
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//
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// Add/Sub
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//
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module add_sub27(add, opa, opb, sum, co);
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input add;
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input [26:0] opa, opb;
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output [26:0] sum;
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output co;
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assign {co, sum} = add ? (opa + opb) : (opa - opb);
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endmodule
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////////////////////////////////////////////////////////////////////////
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//
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// Multiply
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//
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module mul_r2(clk, opa, opb, prod);
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input clk;
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input [23:0] opa, opb;
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output [47:0] prod;
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reg [47:0] prod1, prod;
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always @(posedge clk)
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prod1 <= #1 opa * opb;
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always @(posedge clk)
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prod <= #1 prod1;
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endmodule
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////////////////////////////////////////////////////////////////////////
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//
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// Divide
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//
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module div_r2(clk, opa, opb, quo, rem);
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input clk;
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input [49:0] opa;
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input [23:0] opb;
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output [49:0] quo, rem;
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reg [49:0] quo, rem, quo1, remainder;
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always @(posedge clk)
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quo1 <= #1 opa / opb;
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always @(posedge clk)
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quo <= #1 quo1;
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always @(posedge clk)
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remainder <= #1 opa % opb;
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always @(posedge clk)
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rem <= #1 remainder;
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endmodule
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