This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
5bb7578c91
yosys
/
tests
/
hana
/
test_simulation_xor_1_test.v
4 lines
81 B
Verilog
Raw
Blame
History
module
test
(
input
[
1
:
0
]
in
,
output
out
)
;
assign
out
=
(
in
[
0
]
^
in
[
1
]
)
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink