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15 lines
393 B
Verilog
15 lines
393 B
Verilog
module test (input [2:0] in, output reg [7:0] out);
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always @(in )
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case (in)
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3'b000 : out = 8'b00000001;
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3'b001 : out = 8'b00000010;
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3'b010 : out = 8'b00000100;
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3'b011 : out = 8'b00001000;
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3'b100 : out = 8'b00010000;
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3'b101 : out = 8'b00100000;
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3'b110 : out = 8'b01000000;
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3'b111 : out = 8'b10000000;
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endcase
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endmodule
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