mirror of https://github.com/YosysHQ/yosys.git
1176 lines
40 KiB
Python
1176 lines
40 KiB
Python
#!/usr/bin/env python3
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#
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# yosys -- Yosys Open SYnthesis Suite
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#
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# Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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#
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import os, sys, getopt, re
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##yosys-sys-path##
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from smtio import SmtIo, SmtOpts, MkVcd
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from collections import defaultdict
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got_topt = False
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skip_steps = 0
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step_size = 1
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num_steps = 20
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append_steps = 0
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vcdfile = None
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cexfile = None
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aimfile = None
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aiwfile = None
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aigheader = True
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vlogtbfile = None
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inconstr = list()
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outconstr = None
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gentrace = False
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covermode = False
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tempind = False
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dumpall = False
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assume_skipped = None
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final_only = False
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topmod = None
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noinfo = False
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so = SmtOpts()
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def usage():
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print("""
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yosys-smtbmc [options] <yosys_smt2_output>
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-t <num_steps>
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-t <skip_steps>:<num_steps>
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-t <skip_steps>:<step_size>:<num_steps>
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default: skip_steps=0, step_size=1, num_steps=20
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-g
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generate an arbitrary trace that satisfies
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all assertions and assumptions.
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-i
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instead of BMC run temporal induction
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-c
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instead of regular BMC run cover analysis
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-m <module_name>
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name of the top module
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--smtc <constr_filename>
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read constraints file
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--cex <cex_filename>
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read cex file as written by ABC's "write_cex -n"
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--aig <prefix>
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read AIGER map file (as written by Yosys' "write_aiger -map")
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and AIGER witness file. The file names are <prefix>.aim for
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the map file and <prefix>.aiw for the witness file.
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--aig <aim_filename>:<aiw_filename>
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like above, but for map files and witness files that do not
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share a filename prefix (or use differen file extensions).
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--aig-noheader
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the AIGER witness file does not include the status and
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properties lines.
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--noinfo
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only run the core proof, do not collect and print any
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additional information (e.g. which assert failed)
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--final-only
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only check final constraints, assume base case
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--assume-skipped <start_step>
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assume asserts in skipped steps in BMC.
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no assumptions are created for skipped steps
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before <start_step>.
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--dump-vcd <vcd_filename>
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write trace to this VCD file
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(hint: use 'write_smt2 -wires' for maximum
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coverage of signals in generated VCD file)
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--dump-vlogtb <verilog_filename>
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write trace as Verilog test bench
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--dump-smtc <constr_filename>
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write trace as constraints file
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--dump-all
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when using -g or -i, create a dump file for each
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step. The character '%' is replaces in all dump
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filenames with the step number.
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--append <num_steps>
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add <num_steps> time steps at the end of the trace
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when creating a counter example (this additional time
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steps will still be constrained by assumtions)
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""" + so.helpmsg())
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sys.exit(1)
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try:
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opts, args = getopt.getopt(sys.argv[1:], so.shortopts + "t:igcm:", so.longopts +
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["final-only", "assume-skipped=", "smtc=", "cex=", "aig=", "aig-noheader",
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"dump-vcd=", "dump-vlogtb=", "dump-smtc=", "dump-all", "noinfo", "append="])
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except:
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usage()
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for o, a in opts:
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if o == "-t":
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got_topt = True
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a = a.split(":")
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if len(a) == 1:
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num_steps = int(a[0])
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elif len(a) == 2:
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skip_steps = int(a[0])
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num_steps = int(a[1])
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elif len(a) == 3:
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skip_steps = int(a[0])
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step_size = int(a[1])
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num_steps = int(a[2])
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else:
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assert False
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elif o == "--assume-skipped":
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assume_skipped = int(a)
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elif o == "--final-only":
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final_only = True
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elif o == "--smtc":
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inconstr.append(a)
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elif o == "--cex":
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cexfile = a
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elif o == "--aig":
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if ":" in a:
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aimfile, aiwfile = a.split(":")
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else:
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aimfile = a + ".aim"
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aiwfile = a + ".aiw"
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elif o == "--aig-noheader":
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aigheader = False
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elif o == "--dump-vcd":
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vcdfile = a
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elif o == "--dump-vlogtb":
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vlogtbfile = a
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elif o == "--dump-smtc":
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outconstr = a
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elif o == "--dump-all":
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dumpall = True
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elif o == "--noinfo":
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noinfo = True
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elif o == "--append":
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append_steps = int(a)
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elif o == "-i":
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tempind = True
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elif o == "-g":
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gentrace = True
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elif o == "-c":
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covermode = True
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elif o == "-m":
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topmod = a
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elif so.handle(o, a):
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pass
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else:
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usage()
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if len(args) != 1:
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usage()
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if sum([tempind, gentrace, covermode]) > 1:
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usage()
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constr_final_start = None
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constr_asserts = defaultdict(list)
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constr_assumes = defaultdict(list)
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constr_write = list()
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for fn in inconstr:
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current_states = None
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current_line = 0
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with open(fn, "r") as f:
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for line in f:
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current_line += 1
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if line.startswith("#"):
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continue
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tokens = line.split()
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if len(tokens) == 0:
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continue
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if tokens[0] == "initial":
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current_states = set()
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if not tempind:
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current_states.add(0)
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continue
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if tokens[0] == "final":
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constr_final = True
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if len(tokens) == 1:
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current_states = set(["final-%d" % i for i in range(0, num_steps+1)])
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constr_final_start = 0
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elif len(tokens) == 2:
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arg = abs(int(tokens[1]))
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current_states = set(["final-%d" % i for i in range(arg, num_steps+1)])
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constr_final_start = arg if constr_final_start is None else min(constr_final_start, arg)
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else:
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assert False
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continue
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if tokens[0] == "state":
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current_states = set()
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if not tempind:
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for token in tokens[1:]:
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tok = token.split(":")
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if len(tok) == 1:
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current_states.add(int(token))
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elif len(tok) == 2:
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lower = int(tok[0])
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if tok[1] == "*":
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upper = num_steps
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else:
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upper = int(tok[1])
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for i in range(lower, upper+1):
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current_states.add(i)
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else:
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assert False
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continue
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if tokens[0] == "always":
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if len(tokens) == 1:
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current_states = set(range(0, num_steps+1))
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elif len(tokens) == 2:
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arg = abs(int(tokens[1]))
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current_states = set(range(arg, num_steps+1))
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else:
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assert False
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continue
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if tokens[0] == "assert":
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assert current_states is not None
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for state in current_states:
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constr_asserts[state].append(("%s:%d" % (fn, current_line), " ".join(tokens[1:])))
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continue
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if tokens[0] == "assume":
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assert current_states is not None
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for state in current_states:
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constr_assumes[state].append(("%s:%d" % (fn, current_line), " ".join(tokens[1:])))
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continue
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if tokens[0] == "write":
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constr_write.append(" ".join(tokens[1:]))
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continue
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if tokens[0] == "logic":
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so.logic = " ".join(tokens[1:])
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continue
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assert False
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def get_constr_expr(db, state, final=False, getvalues=False):
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if final:
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if ("final-%d" % state) not in db:
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return ([], [], []) if getvalues else "true"
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else:
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if state not in db:
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return ([], [], []) if getvalues else "true"
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netref_regex = re.compile(r'(^|[( ])\[(-?[0-9]+:|)([^\]]*)\](?=[ )]|$)')
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def replace_netref(match):
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state_sel = match.group(2)
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if state_sel == "":
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st = state
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elif state_sel[0] == "-":
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st = state + int(state_sel[:-1])
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else:
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st = int(state_sel[:-1])
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expr = smt.net_expr(topmod, "s%d" % st, smt.get_path(topmod, match.group(3)))
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return match.group(1) + expr
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expr_list = list()
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for loc, expr in db[("final-%d" % state) if final else state]:
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actual_expr = netref_regex.sub(replace_netref, expr)
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if getvalues:
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expr_list.append((loc, expr, actual_expr))
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else:
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expr_list.append(actual_expr)
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if getvalues:
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loc_list, expr_list, acual_expr_list = zip(*expr_list)
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value_list = smt.get_list(acual_expr_list)
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return loc_list, expr_list, value_list
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if len(expr_list) == 0:
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return "true"
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if len(expr_list) == 1:
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return expr_list[0]
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return "(and %s)" % " ".join(expr_list)
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smt = SmtIo(opts=so)
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if noinfo and vcdfile is None and vlogtbfile is None and outconstr is None:
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smt.produce_models = False
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def print_msg(msg):
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print("%s %s" % (smt.timestamp(), msg))
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sys.stdout.flush()
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print_msg("Solver: %s" % (so.solver))
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with open(args[0], "r") as f:
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for line in f:
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smt.write(line)
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for line in constr_write:
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smt.write(line)
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if topmod is None:
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topmod = smt.topmod
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assert topmod is not None
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assert topmod in smt.modinfo
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if cexfile is not None:
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if not got_topt:
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assume_skipped = 0
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skip_steps = 0
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num_steps = 0
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with open(cexfile, "r") as f:
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cex_regex = re.compile(r'([^\[@=]+)(\[\d+\])?([^@=]*)(@\d+)=([01])')
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for entry in f.read().split():
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match = cex_regex.match(entry)
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assert match
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name, bit, extra_name, step, val = match.group(1), match.group(2), match.group(3), match.group(4), match.group(5)
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if extra_name != "":
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continue
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if name not in smt.modinfo[topmod].inputs:
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continue
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if bit is None:
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bit = 0
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else:
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bit = int(bit[1:-1])
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step = int(step[1:])
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val = int(val)
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if smt.modinfo[topmod].wsize[name] == 1:
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assert bit == 0
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smtexpr = "(= [%s] %s)" % (name, "true" if val else "false")
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else:
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smtexpr = "(= ((_ extract %d %d) [%s]) #b%d)" % (bit, bit, name, val)
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# print("cex@%d: %s" % (step, smtexpr))
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constr_assumes[step].append((cexfile, smtexpr))
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if not got_topt:
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skip_steps = max(skip_steps, step)
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num_steps = max(num_steps, step+1)
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if aimfile is not None:
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input_map = dict()
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init_map = dict()
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latch_map = dict()
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if not got_topt:
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assume_skipped = 0
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skip_steps = 0
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num_steps = 0
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with open(aimfile, "r") as f:
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for entry in f.read().splitlines():
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entry = entry.split()
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if entry[0] == "input":
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input_map[int(entry[1])] = (entry[3], int(entry[2]))
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continue
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if entry[0] == "init":
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init_map[int(entry[1])] = (entry[3], int(entry[2]))
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continue
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if entry[0] in ["latch", "invlatch"]:
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latch_map[int(entry[1])] = (entry[3], int(entry[2]), entry[0] == "invlatch")
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continue
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if entry[0] in ["output", "wire"]:
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continue
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assert False
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with open(aiwfile, "r") as f:
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got_state = False
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got_ffinit = False
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step = 0
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if not aigheader:
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got_state = True
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for entry in f.read().splitlines():
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if len(entry) == 0 or entry[0] in "bcjfu.":
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continue
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if not got_state:
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got_state = True
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assert entry == "1"
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continue
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if not got_ffinit:
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got_ffinit = True
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if len(init_map) == 0:
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for i in range(len(entry)):
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if entry[i] == "x":
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continue
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if i in latch_map:
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value = int(entry[i])
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name = latch_map[i][0]
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bitidx = latch_map[i][1]
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invert = latch_map[i][2]
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if invert:
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value = 1 - value
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path = smt.get_path(topmod, name)
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width = smt.net_width(topmod, path)
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if width == 1:
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assert bitidx == 0
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smtexpr = "(= [%s] %s)" % (name, "true" if value else "false")
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else:
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smtexpr = "(= ((_ extract %d %d) [%s]) #b%d)" % (bitidx, bitidx, name, value)
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constr_assumes[0].append((cexfile, smtexpr))
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continue
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for i in range(len(entry)):
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if entry[i] == "x":
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continue
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if (step == 0) and (i in init_map):
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value = int(entry[i])
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name = init_map[i][0]
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bitidx = init_map[i][1]
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path = smt.get_path(topmod, name)
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if not smt.net_exists(topmod, path):
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match = re.match(r"(.*)\[(\d+)\]$", path[-1])
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if match:
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path[-1] = match.group(1)
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addr = int(match.group(2))
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if not match or not smt.mem_exists(topmod, path):
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print_msg("Ignoring init value for unknown net: %s" % (name))
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continue
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meminfo = smt.mem_info(topmod, path)
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smtexpr = "(select [%s] #b%s)" % (".".join(path), bin(addr)[2:].zfill(meminfo[0]))
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width = meminfo[1]
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else:
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smtexpr = "[%s]" % name
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width = smt.net_width(topmod, path)
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if width == 1:
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assert bitidx == 0
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smtexpr = "(= %s %s)" % (smtexpr, "true" if value else "false")
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else:
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smtexpr = "(= ((_ extract %d %d) %s) #b%d)" % (bitidx, bitidx, smtexpr, value)
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constr_assumes[0].append((cexfile, smtexpr))
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if i in input_map:
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value = int(entry[i])
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name = input_map[i][0]
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bitidx = input_map[i][1]
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path = smt.get_path(topmod, name)
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width = smt.net_width(topmod, path)
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if width == 1:
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assert bitidx == 0
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smtexpr = "(= [%s] %s)" % (name, "true" if value else "false")
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else:
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smtexpr = "(= ((_ extract %d %d) [%s]) #b%d)" % (bitidx, bitidx, name, value)
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constr_assumes[step].append((cexfile, smtexpr))
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if not got_topt:
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skip_steps = max(skip_steps, step)
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num_steps = max(num_steps, step+1)
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step += 1
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def write_vcd_trace(steps_start, steps_stop, index):
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filename = vcdfile.replace("%", index)
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print_msg("Writing trace to VCD file: %s" % (filename))
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with open(filename, "w") as vcd_file:
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vcd = MkVcd(vcd_file)
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path_list = list()
|
|
|
|
for netpath in sorted(smt.hiernets(topmod)):
|
|
hidden_net = False
|
|
for n in netpath:
|
|
if n.startswith("$"):
|
|
hidden_net = True
|
|
if not hidden_net:
|
|
vcd.add_net([topmod] + netpath, smt.net_width(topmod, netpath))
|
|
path_list.append(netpath)
|
|
|
|
mem_trace_data = dict()
|
|
for mempath in sorted(smt.hiermems(topmod)):
|
|
abits, width, rports, wports = smt.mem_info(topmod, mempath)
|
|
|
|
expr_id = list()
|
|
expr_list = list()
|
|
for i in range(steps_start, steps_stop):
|
|
for j in range(rports):
|
|
expr_id.append(('R', i-steps_start, j, 'A'))
|
|
expr_id.append(('R', i-steps_start, j, 'D'))
|
|
expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dA" % j))
|
|
expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dD" % j))
|
|
for j in range(wports):
|
|
expr_id.append(('W', i-steps_start, j, 'A'))
|
|
expr_id.append(('W', i-steps_start, j, 'D'))
|
|
expr_id.append(('W', i-steps_start, j, 'M'))
|
|
expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dA" % j))
|
|
expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dD" % j))
|
|
expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dM" % j))
|
|
|
|
rdata = list()
|
|
wdata = list()
|
|
addrs = set()
|
|
|
|
for eid, edat in zip(expr_id, smt.get_list(expr_list)):
|
|
t, i, j, f = eid
|
|
|
|
if t == 'R':
|
|
c = rdata
|
|
elif t == 'W':
|
|
c = wdata
|
|
else:
|
|
assert False
|
|
|
|
while len(c) <= i:
|
|
c.append(list())
|
|
c = c[i]
|
|
|
|
while len(c) <= j:
|
|
c.append(dict())
|
|
c = c[j]
|
|
|
|
c[f] = smt.bv2bin(edat)
|
|
|
|
if f == 'A':
|
|
addrs.add(c[f])
|
|
|
|
for addr in addrs:
|
|
tdata = list()
|
|
data = ["x"] * width
|
|
gotread = False
|
|
|
|
assert len(rdata) == len(wdata)
|
|
|
|
for i in range(len(wdata)):
|
|
if not gotread:
|
|
for j_data in rdata[i]:
|
|
if j_data["A"] == addr:
|
|
data = list(j_data["D"])
|
|
gotread = True
|
|
break
|
|
|
|
if gotread:
|
|
buf = data[:]
|
|
for i in reversed(range(len(tdata))):
|
|
for k in range(width):
|
|
if tdata[i][k] == "x":
|
|
tdata[i][k] = buf[k]
|
|
else:
|
|
buf[k] = tdata[i][k]
|
|
|
|
tdata.append(data[:])
|
|
|
|
for j_data in wdata[i]:
|
|
if j_data["A"] != addr:
|
|
continue
|
|
|
|
D = j_data["D"]
|
|
M = j_data["M"]
|
|
|
|
for k in range(width):
|
|
if M[k] == "1":
|
|
data[k] = D[k]
|
|
|
|
assert len(tdata) == len(rdata)
|
|
|
|
netpath = mempath[:]
|
|
netpath[-1] += "<%0*x>" % ((len(addr)+3) // 4, int(addr, 2))
|
|
vcd.add_net([topmod] + netpath, width)
|
|
|
|
for i in range(steps_start, steps_stop):
|
|
if i not in mem_trace_data:
|
|
mem_trace_data[i] = list()
|
|
mem_trace_data[i].append((netpath, "".join(tdata[i-steps_start])))
|
|
|
|
for i in range(steps_start, steps_stop):
|
|
vcd.set_time(i)
|
|
value_list = smt.get_net_bin_list(topmod, path_list, "s%d" % i)
|
|
for path, value in zip(path_list, value_list):
|
|
vcd.set_net([topmod] + path, value)
|
|
if i in mem_trace_data:
|
|
for path, value in mem_trace_data[i]:
|
|
vcd.set_net([topmod] + path, value)
|
|
|
|
vcd.set_time(steps_stop)
|
|
|
|
|
|
def write_vlogtb_trace(steps_start, steps_stop, index):
|
|
filename = vlogtbfile.replace("%", index)
|
|
print_msg("Writing trace to Verilog testbench: %s" % (filename))
|
|
|
|
with open(filename, "w") as f:
|
|
print("module testbench;", file=f)
|
|
print(" reg [4095:0] vcdfile;", file=f)
|
|
print(" reg clock = 0, genclock = 1;", file=f)
|
|
|
|
primary_inputs = list()
|
|
clock_inputs = set()
|
|
|
|
for name in smt.modinfo[topmod].inputs:
|
|
if name in ["clk", "clock", "CLK", "CLOCK"]:
|
|
clock_inputs.add(name)
|
|
width = smt.modinfo[topmod].wsize[name]
|
|
primary_inputs.append((name, width))
|
|
|
|
for name, width in primary_inputs:
|
|
if name in clock_inputs:
|
|
print(" wire [%d:0] PI_%s = clock;" % (width-1, name), file=f)
|
|
else:
|
|
print(" reg [%d:0] PI_%s;" % (width-1, name), file=f)
|
|
|
|
print(" %s UUT (" % topmod, file=f)
|
|
print(",\n".join(" .{name}(PI_{name})".format(name=name) for name, _ in primary_inputs), file=f)
|
|
print(" );", file=f)
|
|
|
|
print(" initial begin", file=f)
|
|
print(" if ($value$plusargs(\"vcd=%s\", vcdfile)) begin", file=f)
|
|
print(" $dumpfile(vcdfile);", file=f)
|
|
print(" $dumpvars(0, testbench);", file=f)
|
|
print(" end", file=f)
|
|
print(" while (genclock) begin", file=f)
|
|
print(" #5; clock = 0;", file=f)
|
|
print(" #5; clock = 1;", file=f)
|
|
print(" end", file=f)
|
|
print(" end", file=f)
|
|
|
|
print(" initial begin", file=f)
|
|
|
|
regs = sorted(smt.hiernets(topmod, regs_only=True))
|
|
regvals = smt.get_net_bin_list(topmod, regs, "s%d" % steps_start)
|
|
|
|
print(" #1;", file=f)
|
|
for reg, val in zip(regs, regvals):
|
|
hidden_net = False
|
|
for n in reg:
|
|
if n.startswith("$"):
|
|
hidden_net = True
|
|
print(" %sUUT.%s = %d'b%s;" % ("// " if hidden_net else "", ".".join(reg), len(val), val), file=f)
|
|
|
|
anyconsts = sorted(smt.hieranyconsts(topmod))
|
|
for info in anyconsts:
|
|
if info[3] is not None:
|
|
modstate = smt.net_expr(topmod, "s%d" % steps_start, info[0])
|
|
value = smt.bv2bin(smt.get("(|%s| %s)" % (info[1], modstate)))
|
|
print(" UUT.%s = %d'b%s;" % (".".join(info[0] + [info[3]]), len(value), value), file=f);
|
|
|
|
mems = sorted(smt.hiermems(topmod))
|
|
for mempath in mems:
|
|
abits, width, rports, wports = smt.mem_info(topmod, mempath)
|
|
|
|
addr_expr_list = list()
|
|
data_expr_list = list()
|
|
for i in range(steps_start, steps_stop):
|
|
for j in range(rports):
|
|
addr_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dA" % j))
|
|
data_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dD" % j))
|
|
|
|
addr_list = smt.get_list(addr_expr_list)
|
|
data_list = smt.get_list(data_expr_list)
|
|
|
|
addr_data = dict()
|
|
for addr, data in zip(addr_list, data_list):
|
|
addr = smt.bv2bin(addr)
|
|
data = smt.bv2bin(data)
|
|
if addr not in addr_data:
|
|
addr_data[addr] = data
|
|
|
|
for addr, data in addr_data.items():
|
|
print(" UUT.%s[%d'b%s] = %d'b%s;" % (".".join(mempath), len(addr), addr, len(data), data), file=f)
|
|
|
|
anyseqs = sorted(smt.hieranyseqs(topmod))
|
|
|
|
for i in range(steps_start, steps_stop):
|
|
pi_names = [[name] for name, _ in primary_inputs if name not in clock_inputs]
|
|
pi_values = smt.get_net_bin_list(topmod, pi_names, "s%d" % i)
|
|
|
|
print(" #1;", file=f)
|
|
print(" // state %d" % i, file=f)
|
|
if i > 0:
|
|
print(" @(posedge clock);", file=f)
|
|
for name, val in zip(pi_names, pi_values):
|
|
print(" PI_%s <= %d'b%s;" % (".".join(name), len(val), val), file=f)
|
|
|
|
for info in anyseqs:
|
|
if info[3] is not None:
|
|
modstate = smt.net_expr(topmod, "s%d" % steps_start, info[0])
|
|
value = smt.bv2bin(smt.get("(|%s| %s)" % (info[1], modstate)))
|
|
print(" UUT.%s = %d'b%s;" % (".".join(info[0] + [info[3]]), len(value), value), file=f);
|
|
|
|
print(" genclock = 0;", file=f)
|
|
print(" end", file=f)
|
|
|
|
print("endmodule", file=f)
|
|
|
|
|
|
def write_constr_trace(steps_start, steps_stop, index):
|
|
filename = outconstr.replace("%", index)
|
|
print_msg("Writing trace to constraints file: %s" % (filename))
|
|
|
|
with open(filename, "w") as f:
|
|
primary_inputs = list()
|
|
|
|
for name in smt.modinfo[topmod].inputs:
|
|
width = smt.modinfo[topmod].wsize[name]
|
|
primary_inputs.append((name, width))
|
|
|
|
if steps_start == 0:
|
|
print("initial", file=f)
|
|
else:
|
|
print("state %d" % steps_start, file=f)
|
|
|
|
regnames = sorted(smt.hiernets(topmod, regs_only=True))
|
|
regvals = smt.get_net_list(topmod, regnames, "s%d" % steps_start)
|
|
|
|
for name, val in zip(regnames, regvals):
|
|
print("assume (= [%s] %s)" % (".".join(name), val), file=f)
|
|
|
|
mems = sorted(smt.hiermems(topmod))
|
|
for mempath in mems:
|
|
abits, width, rports, wports = smt.mem_info(topmod, mempath)
|
|
|
|
addr_expr_list = list()
|
|
data_expr_list = list()
|
|
for i in range(steps_start, steps_stop):
|
|
for j in range(rports):
|
|
addr_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dA" % j))
|
|
data_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dD" % j))
|
|
|
|
addr_list = smt.get_list(addr_expr_list)
|
|
data_list = smt.get_list(data_expr_list)
|
|
|
|
addr_data = dict()
|
|
for addr, data in zip(addr_list, data_list):
|
|
if addr not in addr_data:
|
|
addr_data[addr] = data
|
|
|
|
for addr, data in addr_data.items():
|
|
print("assume (= (select [%s] %s) %s)" % (".".join(mempath), addr, data), file=f)
|
|
|
|
for k in range(steps_start, steps_stop):
|
|
print("", file=f)
|
|
print("state %d" % k, file=f)
|
|
|
|
pi_names = [[name] for name, _ in sorted(primary_inputs)]
|
|
pi_values = smt.get_net_list(topmod, pi_names, "s%d" % k)
|
|
|
|
for name, val in zip(pi_names, pi_values):
|
|
print("assume (= [%s] %s)" % (".".join(name), val), file=f)
|
|
|
|
|
|
def write_trace(steps_start, steps_stop, index):
|
|
if vcdfile is not None:
|
|
write_vcd_trace(steps_start, steps_stop, index)
|
|
|
|
if vlogtbfile is not None:
|
|
write_vlogtb_trace(steps_start, steps_stop, index)
|
|
|
|
if outconstr is not None:
|
|
write_constr_trace(steps_start, steps_stop, index)
|
|
|
|
|
|
def print_failed_asserts_worker(mod, state, path, extrainfo):
|
|
assert mod in smt.modinfo
|
|
found_failed_assert = False
|
|
|
|
if smt.get("(|%s_a| %s)" % (mod, state)) in ["true", "#b1"]:
|
|
return
|
|
|
|
for cellname, celltype in smt.modinfo[mod].cells.items():
|
|
if print_failed_asserts_worker(celltype, "(|%s_h %s| %s)" % (mod, cellname, state), path + "." + cellname, extrainfo):
|
|
found_failed_assert = True
|
|
|
|
for assertfun, assertinfo in smt.modinfo[mod].asserts.items():
|
|
if smt.get("(|%s| %s)" % (assertfun, state)) in ["false", "#b0"]:
|
|
print_msg("Assert failed in %s: %s%s" % (path, assertinfo, extrainfo))
|
|
found_failed_assert = True
|
|
|
|
return found_failed_assert
|
|
|
|
|
|
def print_failed_asserts(state, final=False, extrainfo=""):
|
|
if noinfo: return
|
|
loc_list, expr_list, value_list = get_constr_expr(constr_asserts, state, final=final, getvalues=True)
|
|
found_failed_assert = False
|
|
|
|
for loc, expr, value in zip(loc_list, expr_list, value_list):
|
|
if smt.bv2int(value) == 0:
|
|
print_msg("Assert %s failed: %s%s" % (loc, expr, extrainfo))
|
|
found_failed_assert = True
|
|
|
|
if not final:
|
|
if print_failed_asserts_worker(topmod, "s%d" % state, topmod, extrainfo):
|
|
found_failed_assert = True
|
|
|
|
return found_failed_assert
|
|
|
|
|
|
def print_anyconsts_worker(mod, state, path):
|
|
assert mod in smt.modinfo
|
|
|
|
for cellname, celltype in smt.modinfo[mod].cells.items():
|
|
print_anyconsts_worker(celltype, "(|%s_h %s| %s)" % (mod, cellname, state), path + "." + cellname)
|
|
|
|
for fun, info in smt.modinfo[mod].anyconsts.items():
|
|
if info[1] is None:
|
|
print_msg("Value for anyconst in %s (%s): %d" % (path, info, smt.bv2int(smt.get("(|%s| %s)" % (fun, state)))))
|
|
else:
|
|
print_msg("Value for anyconst %s.%s (%s): %d" % (path, info[1], info[0], smt.bv2int(smt.get("(|%s| %s)" % (fun, state)))))
|
|
|
|
|
|
def print_anyconsts(state):
|
|
if noinfo: return
|
|
print_anyconsts_worker(topmod, "s%d" % state, topmod)
|
|
|
|
|
|
def get_cover_list(mod, base):
|
|
assert mod in smt.modinfo
|
|
|
|
cover_expr = list()
|
|
cover_desc = list()
|
|
|
|
for expr, desc in smt.modinfo[mod].covers.items():
|
|
cover_expr.append("(ite (|%s| %s) #b1 #b0)" % (expr, base))
|
|
cover_desc.append(desc)
|
|
|
|
for cell, submod in smt.modinfo[mod].cells.items():
|
|
e, d = get_cover_list(submod, "(|%s_h %s| %s)" % (mod, cell, base))
|
|
cover_expr += e
|
|
cover_desc += d
|
|
|
|
return cover_expr, cover_desc
|
|
|
|
|
|
if tempind:
|
|
retstatus = False
|
|
skip_counter = step_size
|
|
for step in range(num_steps, -1, -1):
|
|
smt.write("(declare-fun s%d () |%s_s|)" % (step, topmod))
|
|
smt.write("(assert (|%s_u| s%d))" % (topmod, step))
|
|
smt.write("(assert (|%s_h| s%d))" % (topmod, step))
|
|
smt.write("(assert (not (|%s_is| s%d)))" % (topmod, step))
|
|
smt.write("(assert %s)" % get_constr_expr(constr_assumes, step))
|
|
|
|
if step == num_steps:
|
|
smt.write("(assert (not (and (|%s_a| s%d) %s)))" % (topmod, step, get_constr_expr(constr_asserts, step)))
|
|
|
|
else:
|
|
smt.write("(assert (|%s_t| s%d s%d))" % (topmod, step, step+1))
|
|
smt.write("(assert (|%s_a| s%d))" % (topmod, step))
|
|
smt.write("(assert %s)" % get_constr_expr(constr_asserts, step))
|
|
|
|
if step > num_steps-skip_steps:
|
|
print_msg("Skipping induction in step %d.." % (step))
|
|
continue
|
|
|
|
skip_counter += 1
|
|
if skip_counter < step_size:
|
|
print_msg("Skipping induction in step %d.." % (step))
|
|
continue
|
|
|
|
skip_counter = 0
|
|
print_msg("Trying induction in step %d.." % (step))
|
|
|
|
if smt.check_sat() == "sat":
|
|
if step == 0:
|
|
print("%s Temporal induction failed!" % smt.timestamp())
|
|
print_anyconsts(num_steps)
|
|
print_failed_asserts(num_steps)
|
|
write_trace(step, num_steps+1, '%')
|
|
|
|
elif dumpall:
|
|
print_anyconsts(num_steps)
|
|
print_failed_asserts(num_steps)
|
|
write_trace(step, num_steps+1, "%d" % step)
|
|
|
|
else:
|
|
print("%s Temporal induction successful." % smt.timestamp())
|
|
retstatus = True
|
|
break
|
|
|
|
elif covermode:
|
|
cover_expr, cover_desc = get_cover_list(topmod, "state")
|
|
cover_mask = "1" * len(cover_desc)
|
|
|
|
if len(cover_expr) > 1:
|
|
cover_expr = "(concat %s)" % " ".join(cover_expr)
|
|
elif len(cover_expr) == 1:
|
|
cover_expr = cover_expr[0]
|
|
else:
|
|
cover_expr = "#b0"
|
|
|
|
coveridx = 0
|
|
smt.write("(define-fun covers_0 ((state |%s_s|)) (_ BitVec %d) %s)" % (topmod, len(cover_desc), cover_expr))
|
|
|
|
step = 0
|
|
retstatus = False
|
|
found_failed_assert = False
|
|
|
|
assert step_size == 1
|
|
|
|
while step < num_steps:
|
|
smt.write("(declare-fun s%d () |%s_s|)" % (step, topmod))
|
|
smt.write("(assert (|%s_u| s%d))" % (topmod, step))
|
|
smt.write("(assert (|%s_h| s%d))" % (topmod, step))
|
|
smt.write("(assert %s)" % get_constr_expr(constr_assumes, step))
|
|
|
|
if step == 0:
|
|
smt.write("(assert (|%s_i| s0))" % (topmod))
|
|
smt.write("(assert (|%s_is| s0))" % (topmod))
|
|
|
|
else:
|
|
smt.write("(assert (|%s_t| s%d s%d))" % (topmod, step-1, step))
|
|
smt.write("(assert (not (|%s_is| s%d)))" % (topmod, step))
|
|
|
|
while "1" in cover_mask:
|
|
print_msg("Checking cover reachability in step %d.." % (step))
|
|
smt.write("(push 1)")
|
|
smt.write("(assert (distinct (covers_%d s%d) #b%s))" % (coveridx, step, "0" * len(cover_desc)))
|
|
|
|
if smt.check_sat() == "unsat":
|
|
smt.write("(pop 1)")
|
|
break
|
|
|
|
if append_steps > 0:
|
|
for i in range(step+1, step+1+append_steps):
|
|
print_msg("Appending additional step %d." % i)
|
|
smt.write("(declare-fun s%d () |%s_s|)" % (i, topmod))
|
|
smt.write("(assert (not (|%s_is| s%d)))" % (topmod, i))
|
|
smt.write("(assert (|%s_u| s%d))" % (topmod, i))
|
|
smt.write("(assert (|%s_h| s%d))" % (topmod, i))
|
|
smt.write("(assert (|%s_t| s%d s%d))" % (topmod, i-1, i))
|
|
smt.write("(assert %s)" % get_constr_expr(constr_assumes, i))
|
|
print_msg("Re-solving with appended steps..")
|
|
assert smt.check_sat() == "sat"
|
|
|
|
reached_covers = smt.bv2bin(smt.get("(covers_%d s%d)" % (coveridx, step)))
|
|
assert len(reached_covers) == len(cover_desc)
|
|
|
|
new_cover_mask = []
|
|
|
|
for i in range(len(reached_covers)):
|
|
if reached_covers[i] == "0":
|
|
new_cover_mask.append(cover_mask[i])
|
|
continue
|
|
|
|
print_msg("Reached cover statement at %s in step %d." % (cover_desc[i], step))
|
|
new_cover_mask.append("0")
|
|
|
|
cover_mask = "".join(new_cover_mask)
|
|
|
|
for i in range(step+1+append_steps):
|
|
if print_failed_asserts(i, extrainfo=" (step %d)" % i):
|
|
found_failed_assert = True
|
|
|
|
write_trace(0, step+1+append_steps, "%d" % coveridx)
|
|
|
|
if found_failed_assert:
|
|
break
|
|
|
|
coveridx += 1
|
|
smt.write("(pop 1)")
|
|
smt.write("(define-fun covers_%d ((state |%s_s|)) (_ BitVec %d) (bvand (covers_%d state) #b%s))" % (coveridx, topmod, len(cover_desc), coveridx-1, cover_mask))
|
|
|
|
if found_failed_assert:
|
|
break
|
|
|
|
if "1" not in cover_mask:
|
|
retstatus = True
|
|
break
|
|
|
|
step += 1
|
|
|
|
if "1" in cover_mask:
|
|
for i in range(len(cover_mask)):
|
|
if cover_mask[i] == "1":
|
|
print_msg("Unreached cover statement at %s." % cover_desc[i])
|
|
|
|
else: # not tempind, covermode
|
|
step = 0
|
|
retstatus = True
|
|
while step < num_steps:
|
|
smt.write("(declare-fun s%d () |%s_s|)" % (step, topmod))
|
|
smt.write("(assert (|%s_u| s%d))" % (topmod, step))
|
|
smt.write("(assert (|%s_h| s%d))" % (topmod, step))
|
|
smt.write("(assert %s)" % get_constr_expr(constr_assumes, step))
|
|
|
|
if step == 0:
|
|
smt.write("(assert (|%s_i| s0))" % (topmod))
|
|
smt.write("(assert (|%s_is| s0))" % (topmod))
|
|
|
|
else:
|
|
smt.write("(assert (|%s_t| s%d s%d))" % (topmod, step-1, step))
|
|
smt.write("(assert (not (|%s_is| s%d)))" % (topmod, step))
|
|
|
|
if step < skip_steps:
|
|
if assume_skipped is not None and step >= assume_skipped:
|
|
print_msg("Skipping step %d (and assuming pass).." % (step))
|
|
smt.write("(assert (|%s_a| s%d))" % (topmod, step))
|
|
smt.write("(assert %s)" % get_constr_expr(constr_asserts, step))
|
|
else:
|
|
print_msg("Skipping step %d.." % (step))
|
|
step += 1
|
|
continue
|
|
|
|
last_check_step = step
|
|
for i in range(1, step_size):
|
|
if step+i < num_steps:
|
|
smt.write("(declare-fun s%d () |%s_s|)" % (step+i, topmod))
|
|
smt.write("(assert (not (|%s_is| s%d)))" % (topmod, step+i))
|
|
smt.write("(assert (|%s_u| s%d))" % (topmod, step+i))
|
|
smt.write("(assert (|%s_h| s%d))" % (topmod, step+i))
|
|
smt.write("(assert (|%s_t| s%d s%d))" % (topmod, step+i-1, step+i))
|
|
smt.write("(assert %s)" % get_constr_expr(constr_assumes, step+i))
|
|
last_check_step = step+i
|
|
|
|
if not gentrace:
|
|
if not final_only:
|
|
if last_check_step == step:
|
|
print_msg("Checking asserts in step %d.." % (step))
|
|
else:
|
|
print_msg("Checking asserts in steps %d to %d.." % (step, last_check_step))
|
|
smt.write("(push 1)")
|
|
|
|
smt.write("(assert (not (and %s)))" % " ".join(["(|%s_a| s%d)" % (topmod, i) for i in range(step, last_check_step+1)] +
|
|
[get_constr_expr(constr_asserts, i) for i in range(step, last_check_step+1)]))
|
|
|
|
if smt.check_sat() == "sat":
|
|
print("%s BMC failed!" % smt.timestamp())
|
|
if append_steps > 0:
|
|
for i in range(last_check_step+1, last_check_step+1+append_steps):
|
|
print_msg("Appending additional step %d." % i)
|
|
smt.write("(declare-fun s%d () |%s_s|)" % (i, topmod))
|
|
smt.write("(assert (not (|%s_is| s%d)))" % (topmod, i))
|
|
smt.write("(assert (|%s_u| s%d))" % (topmod, i))
|
|
smt.write("(assert (|%s_h| s%d))" % (topmod, i))
|
|
smt.write("(assert (|%s_t| s%d s%d))" % (topmod, i-1, i))
|
|
smt.write("(assert %s)" % get_constr_expr(constr_assumes, i))
|
|
print_msg("Re-solving with appended steps..")
|
|
assert smt.check_sat() == "sat"
|
|
print_anyconsts(step)
|
|
for i in range(step, last_check_step+1):
|
|
print_failed_asserts(i)
|
|
write_trace(0, last_check_step+1+append_steps, '%')
|
|
retstatus = False
|
|
break
|
|
|
|
smt.write("(pop 1)")
|
|
|
|
if (constr_final_start is not None) or (last_check_step+1 != num_steps):
|
|
for i in range(step, last_check_step+1):
|
|
smt.write("(assert (|%s_a| s%d))" % (topmod, i))
|
|
smt.write("(assert %s)" % get_constr_expr(constr_asserts, i))
|
|
|
|
if constr_final_start is not None:
|
|
for i in range(step, last_check_step+1):
|
|
if i < constr_final_start:
|
|
continue
|
|
|
|
print_msg("Checking final constraints in step %d.." % (i))
|
|
smt.write("(push 1)")
|
|
|
|
smt.write("(assert %s)" % get_constr_expr(constr_assumes, i, final=True))
|
|
smt.write("(assert (not %s))" % get_constr_expr(constr_asserts, i, final=True))
|
|
|
|
if smt.check_sat() == "sat":
|
|
print("%s BMC failed!" % smt.timestamp())
|
|
print_anyconsts(i)
|
|
print_failed_asserts(i, final=True)
|
|
write_trace(0, i+1, '%')
|
|
retstatus = False
|
|
break
|
|
|
|
smt.write("(pop 1)")
|
|
if not retstatus:
|
|
break
|
|
|
|
else: # gentrace
|
|
for i in range(step, last_check_step+1):
|
|
smt.write("(assert (|%s_a| s%d))" % (topmod, i))
|
|
smt.write("(assert %s)" % get_constr_expr(constr_asserts, i))
|
|
|
|
print_msg("Solving for step %d.." % (last_check_step))
|
|
if smt.check_sat() != "sat":
|
|
print("%s No solution found!" % smt.timestamp())
|
|
retstatus = False
|
|
break
|
|
|
|
elif dumpall:
|
|
print_anyconsts(0)
|
|
write_trace(0, last_check_step+1, "%d" % step)
|
|
|
|
step += step_size
|
|
|
|
if gentrace:
|
|
print_anyconsts(0)
|
|
write_trace(0, num_steps, '%')
|
|
|
|
|
|
smt.write("(exit)")
|
|
smt.wait()
|
|
|
|
print_msg("Status: %s" % ("PASSED" if retstatus else "FAILED (!)"))
|
|
sys.exit(0 if retstatus else 1)
|