yosys/passes
N. Engelhardt 3e46faa58c
Merge pull request #1763 from boqwxp/issue1762
Closes #1762. Adds warnings for `select` arguments not matching any object and for `add` command when no modules selected
2020-03-23 20:14:13 +01:00
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cmds Merge pull request #1763 from boqwxp/issue1762 2020-03-23 20:14:13 +01:00
equiv xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
fsm fsm_extract: Initialize celltypes with full design. 2020-03-19 18:51:21 +01:00
hierarchy Merge pull request #1519 from YosysHQ/eddie/submod_po 2020-03-03 08:19:06 -08:00
memory Cleanup 2019-12-17 00:25:08 -08:00
opt ystests: fix write_smt2_write_smt2_cyclic_dependency_fail 2020-02-28 12:33:55 -08:00
pmgen Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly 2020-02-02 14:53:32 +00:00
proc proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage 2019-11-21 20:46:41 +00:00
sat Clean up pseudo-private member usage in `passes/sat/miter.cc`. 2020-03-19 07:07:22 +00:00
techmap iopadmap: Attempt to give new wires/cells meaningful names 2020-03-22 23:01:09 +01:00
tests Document (* gentb_skip *) attr for test_autotb 2019-09-18 12:41:35 -07:00