mirror of https://github.com/YosysHQ/yosys.git
181 lines
6.1 KiB
C++
181 lines
6.1 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/celltypes.h"
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#include "fsmdata.h"
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static RTLIL::Module *module;
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static SigMap assign_map;
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typedef std::pair<RTLIL::Cell*,std::string> sig2driver_entry_t;
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static SigSet<sig2driver_entry_t> sig2driver, sig2user;
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static std::set<RTLIL::Cell*> muxtree_cells;
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static SigPool sig_at_port;
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static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig)
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{
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if (sig_at_port.check_any(assign_map(sig)))
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return false;
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if (sig.is_fully_const() || old_sig == sig)
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return true;
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std::set<sig2driver_entry_t> cellport_list;
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sig2driver.find(sig, cellport_list);
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for (auto &cellport : cellport_list) {
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if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y")
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return false;
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RTLIL::SigSpec sig_a = assign_map(cellport.first->connections["\\A"]);
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RTLIL::SigSpec sig_b = assign_map(cellport.first->connections["\\B"]);
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if (!check_state_mux_tree(old_sig, sig_a))
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return false;
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for (int i = 0; i < sig_b.width; i += sig_a.width)
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if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.width)))
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return false;
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muxtree_cells.insert(cellport.first);
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}
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return true;
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}
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static bool check_state_users(RTLIL::SigSpec sig)
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{
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if (sig_at_port.check_any(assign_map(sig)))
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return false;
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std::set<sig2driver_entry_t> cellport_list;
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sig2user.find(sig, cellport_list);
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for (auto &cellport : cellport_list) {
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RTLIL::Cell *cell = cellport.first;
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if (muxtree_cells.count(cell) > 0)
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continue;
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if (cellport.second != "\\A" && cellport.second != "\\B")
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return false;
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if (cell->connections.count("\\A") == 0 || cell->connections.count("\\B") == 0 || cell->connections.count("\\Y") == 0)
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return false;
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for (auto &port_it : cell->connections)
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if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")
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return false;
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if (assign_map(cell->connections["\\A"]) == sig && cell->connections["\\B"].is_fully_const())
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continue;
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if (assign_map(cell->connections["\\B"]) == sig && cell->connections["\\A"].is_fully_const())
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continue;
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return false;
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}
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return true;
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}
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static void detect_fsm(RTLIL::Wire *wire)
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{
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if (wire->attributes.count("\\fsm_encoding") > 0 || wire->width <= 1)
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return;
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if (sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire))))
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return;
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std::set<sig2driver_entry_t> cellport_list;
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sig2driver.find(RTLIL::SigSpec(wire), cellport_list);
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for (auto &cellport : cellport_list) {
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if ((cellport.first->type != "$dff" && cellport.first->type != "$adff") || cellport.second != "\\Q")
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continue;
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muxtree_cells.clear();
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RTLIL::SigSpec sig_q = assign_map(cellport.first->connections["\\Q"]);
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RTLIL::SigSpec sig_d = assign_map(cellport.first->connections["\\D"]);
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if (sig_q == RTLIL::SigSpec(wire) && check_state_mux_tree(sig_q, sig_d) && check_state_users(sig_q)) {
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log("Found FSM state register %s in module %s.\n", wire->name.c_str(), module->name.c_str());
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wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto");
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return;
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}
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}
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}
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struct FsmDetectPass : public Pass {
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FsmDetectPass() : Pass("fsm_detect", "finding FSMs in design") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" fsm_detect [selection]\n");
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log("\n");
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log("This pass detects finite state machines by identifying the state signal.\n");
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log("The state signal is then marked by setting the attribute 'fsm_encoding'\n");
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log("on the state signal to \"auto\".\n");
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log("\n");
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log("Existing 'fsm_encoding' attributes are not changed by this pass.\n");
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log("\n");
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log("Signals can be protected from being detected by this pass by setting the\n");
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log("'fsm_encoding' attribute to \"none\".\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing FSM_DETECT pass (finding FSMs in design).\n");
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extra_args(args, 1, design);
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CellTypes ct;
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ct.setup_internals();
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ct.setup_internals_mem();
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ct.setup_stdcells();
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ct.setup_stdcells_mem();
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for (auto &mod_it : design->modules)
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{
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if (!design->selected(mod_it.second))
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continue;
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module = mod_it.second;
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assign_map.set(module);
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sig2driver.clear();
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sig2user.clear();
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sig_at_port.clear();
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for (auto &cell_it : module->cells)
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for (auto &conn_it : cell_it.second->connections) {
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if (ct.cell_output(cell_it.second->type, conn_it.first)) {
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RTLIL::SigSpec sig = conn_it.second;
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assign_map.apply(sig);
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sig2driver.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first));
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}
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if (!ct.cell_known(cell_it.second->type) || ct.cell_input(cell_it.second->type, conn_it.first)) {
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RTLIL::SigSpec sig = conn_it.second;
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assign_map.apply(sig);
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sig2user.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first));
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}
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}
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for (auto &wire_it : module->wires)
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if (wire_it.second->port_id != 0)
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sig_at_port.add(assign_map(RTLIL::SigSpec(wire_it.second)));
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for (auto &wire_it : module->wires)
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if (design->selected(module, wire_it.second))
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detect_fsm(wire_it.second);
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}
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assign_map.clear();
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sig2driver.clear();
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sig2user.clear();
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muxtree_cells.clear();
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}
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} FsmDetectPass;
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