mirror of https://github.com/YosysHQ/yosys.git
159 lines
5.1 KiB
Verilog
159 lines
5.1 KiB
Verilog
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// See Xilinx UG953 and UG474 for a description of the cell types below.
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// http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
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// http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
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module VCC(output P);
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assign P = 1;
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endmodule
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module GND(output G);
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assign G = 0;
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endmodule
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module IBUF(output O, input I);
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assign O = I;
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endmodule
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module OBUF(output O, input I);
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assign O = I;
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endmodule
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module BUFG(output O, input I);
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assign O = I;
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endmodule
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// module OBUFT(output O, input I, T);
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// assign O = T ? 1'bz : I;
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// endmodule
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// module IOBUF(inout IO, output O, input I, T);
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// assign O = IO, IO = T ? 1'bz : I;
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// endmodule
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module INV(output O, input I);
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assign O = !I;
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endmodule
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module LUT1(output O, input I0);
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parameter [1:0] INIT = 0;
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assign O = I0 ? INIT[1] : INIT[0];
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endmodule
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module LUT2(output O, input I0, I1);
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parameter [3:0] INIT = 0;
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wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT3(output O, input I0, I1, I2);
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parameter [7:0] INIT = 0;
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wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT4(output O, input I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT5(output O, input I0, I1, I2, I3, I4);
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parameter [31:0] INIT = 0;
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wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT6(output O, input I0, I1, I2, I3, I4, I5);
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parameter [63:0] INIT = 0;
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wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
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wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module MUXCY(output O, input CI, DI, S);
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assign O = S ? CI : DI;
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endmodule
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module MUXF7(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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module MUXF8(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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module XORCY(output O, input CI, LI);
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assign O = CI ^ LI;
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endmodule
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module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
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assign O = S ^ {CO[2:0], CI | CYINIT};
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assign CO[0] = S[0] ? CI | CYINIT : DI[0];
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assign CO[1] = S[1] ? CO[0] : DI[1];
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assign CO[2] = S[2] ? CO[1] : DI[2];
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assign CO[3] = S[3] ? CO[2] : DI[3];
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endmodule
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module FDRE (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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initial Q <= INIT;
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generate case (|IS_C_INVERTED)
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1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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endcase endgenerate
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endmodule
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module FDSE (output reg Q, input C, CE, D, S);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_S_INVERTED = 1'b0;
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initial Q <= INIT;
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generate case (|IS_C_INVERTED)
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1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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endcase endgenerate
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endmodule
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module FDCE (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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initial Q <= INIT;
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generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
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2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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endcase endgenerate
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endmodule
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module FDPE (output reg Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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initial Q <= INIT;
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generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
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2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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endcase endgenerate
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endmodule
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