mirror of https://github.com/YosysHQ/yosys.git
438 lines
13 KiB
C++
438 lines
13 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "opt_status.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/celltypes.h"
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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#include <set>
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using RTLIL::id2cstr;
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struct OptMuxtreeWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap assign_map;
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int removed_count;
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typedef std::pair<RTLIL::Wire*,int> bitDef_t;
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struct bitinfo_t {
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int num;
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bitDef_t bit;
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bool seen_non_mux;
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std::vector<int> mux_users;
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std::vector<int> mux_drivers;
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};
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std::map<bitDef_t, int> bit2num;
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std::vector<bitinfo_t> bit2info;
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struct portinfo_t {
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std::vector<int> ctrl_sigs;
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std::vector<int> input_sigs;
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std::vector<int> input_muxes;
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bool const_activated;
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bool enabled;
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};
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struct muxinfo_t {
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RTLIL::Cell *cell;
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std::vector<portinfo_t> ports;
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};
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std::vector<muxinfo_t> mux2info;
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OptMuxtreeWorker(RTLIL::Design *design, RTLIL::Module *module) :
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design(design), module(module), assign_map(module), removed_count(0)
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{
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log("Running muxtree optimizier on module %s..\n", module->name.c_str());
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log(" Creating internal representation of mux trees.\n");
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// Populate bit2info[]:
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// .seen_non_mux
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// .mux_users
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// .mux_drivers
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// Populate mux2info[].ports[]:
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// .ctrl_sigs
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// .input_sigs
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// .const_activated
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for (auto &cell_it : module->cells)
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{
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
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{
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RTLIL::SigSpec sig_a = cell->connections["\\A"];
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RTLIL::SigSpec sig_b = cell->connections["\\B"];
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RTLIL::SigSpec sig_s = cell->connections["\\S"];
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RTLIL::SigSpec sig_y = cell->connections["\\Y"];
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muxinfo_t muxinfo;
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muxinfo.cell = cell;
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for (int i = 0; i < sig_s.width; i++) {
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RTLIL::SigSpec sig = sig_b.extract(i*sig_a.width, sig_a.width);
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RTLIL::SigSpec ctrl_sig = assign_map(sig_s.extract(i, 1));
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portinfo_t portinfo;
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for (int idx : sig2bits(sig)) {
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add_to_list(bit2info[idx].mux_users, mux2info.size());
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add_to_list(portinfo.input_sigs, idx);
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}
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for (int idx : sig2bits(ctrl_sig))
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add_to_list(portinfo.ctrl_sigs, idx);
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portinfo.const_activated = ctrl_sig.is_fully_const() && ctrl_sig.as_bool();
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portinfo.enabled = false;
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muxinfo.ports.push_back(portinfo);
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}
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portinfo_t portinfo;
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for (int idx : sig2bits(sig_a)) {
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add_to_list(bit2info[idx].mux_users, mux2info.size());
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add_to_list(portinfo.input_sigs, idx);
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}
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portinfo.const_activated = false;
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portinfo.enabled = false;
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muxinfo.ports.push_back(portinfo);
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for (int idx : sig2bits(sig_y))
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add_to_list(bit2info[idx].mux_drivers, mux2info.size());
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for (int idx : sig2bits(sig_s))
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bit2info[idx].seen_non_mux = true;
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mux2info.push_back(muxinfo);
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}
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else
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{
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for (auto &it : cell->connections) {
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for (int idx : sig2bits(it.second))
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bit2info[idx].seen_non_mux = true;
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}
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}
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}
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for (auto &it : module->wires) {
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if (it.second->port_output)
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for (int idx : sig2bits(RTLIL::SigSpec(it.second)))
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bit2info[idx].seen_non_mux = true;
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}
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if (mux2info.size() == 0) {
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log(" No muxes found in this module.\n");
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return;
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}
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// Populate mux2info[].ports[]:
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// .input_muxes
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for (size_t i = 0; i < bit2info.size(); i++)
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for (int j : bit2info[i].mux_users)
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for (auto &p : mux2info[j].ports) {
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if (is_in_list(p.input_sigs, i))
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for (int k : bit2info[i].mux_drivers)
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add_to_list(p.input_muxes, k);
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}
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log(" Evaluating internal representation of mux trees.\n");
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std::set<int> root_muxes;
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for (auto &bi : bit2info) {
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if (!bi.seen_non_mux)
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continue;
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for (int mux_idx : bi.mux_drivers)
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root_muxes.insert(mux_idx);
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}
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for (int mux_idx : root_muxes)
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eval_root_mux(mux_idx);
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log(" Analyzing evaluation results.\n");
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for (auto &mi : mux2info)
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{
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std::vector<int> live_ports;
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for (size_t port_idx = 0; port_idx < mi.ports.size(); port_idx++) {
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portinfo_t &pi = mi.ports[port_idx];
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if (pi.enabled) {
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live_ports.push_back(port_idx);
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} else {
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log(" dead port %zd/%zd on %s %s.\n", port_idx+1, mi.ports.size(),
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mi.cell->type.c_str(), mi.cell->name.c_str());
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OPT_DID_SOMETHING = true;
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removed_count++;
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}
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}
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if (live_ports.size() == mi.ports.size())
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continue;
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if (live_ports.size() == 0) {
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module->cells.erase(mi.cell->name);
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delete mi.cell;
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continue;
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}
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RTLIL::SigSpec sig_a = mi.cell->connections["\\A"];
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RTLIL::SigSpec sig_b = mi.cell->connections["\\B"];
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RTLIL::SigSpec sig_s = mi.cell->connections["\\S"];
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RTLIL::SigSpec sig_y = mi.cell->connections["\\Y"];
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RTLIL::SigSpec sig_ports = sig_b;
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sig_ports.append(sig_a);
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if (live_ports.size() == 1)
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{
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RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.width, sig_a.width);
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module->connections.push_back(RTLIL::SigSig(sig_y, sig_in));
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module->cells.erase(mi.cell->name);
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delete mi.cell;
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}
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else
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{
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RTLIL::SigSpec new_sig_a, new_sig_b, new_sig_s;
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for (size_t i = 0; i < live_ports.size(); i++) {
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RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.width, sig_a.width);
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if (i == live_ports.size()-1) {
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new_sig_a = sig_in;
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} else {
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new_sig_b.append(sig_in);
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new_sig_s.append(sig_s.extract(live_ports[i], 1));
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}
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}
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mi.cell->connections["\\A"] = new_sig_a;
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mi.cell->connections["\\B"] = new_sig_b;
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mi.cell->connections["\\S"] = new_sig_s;
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if (new_sig_s.width == 1) {
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mi.cell->type = "$mux";
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mi.cell->attributes.erase("\\S_WIDTH");
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} else {
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mi.cell->attributes["\\S_WIDTH"] = RTLIL::Const(new_sig_s.width);
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}
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}
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}
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}
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bool list_is_subset(const std::vector<int> &sub, const std::vector<int> &super)
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{
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for (int v : sub)
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if (!is_in_list(super, v))
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return false;
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return true;
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}
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bool is_in_list(const std::vector<int> &list, int value)
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{
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for (int v : list)
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if (v == value)
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return true;
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return false;
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}
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void add_to_list(std::vector<int> &list, int value)
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{
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if (!is_in_list(list, value))
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list.push_back(value);
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}
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std::vector<int> sig2bits(RTLIL::SigSpec sig)
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{
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std::vector<int> results;
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assign_map.apply(sig);
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sig.expand();
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for (auto &c : sig.chunks)
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if (c.wire != NULL) {
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bitDef_t bit(c.wire, c.offset);
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if (bit2num.count(bit) == 0) {
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bitinfo_t info;
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info.num = bit2info.size();
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info.bit = bit;
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info.seen_non_mux = false;
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bit2info.push_back(info);
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bit2num[info.bit] = info.num;
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}
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results.push_back(bit2num[bit]);
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}
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return results;
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}
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struct knowledge_t
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{
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// database of known inactive signals
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// the 2nd integer is a reference counter used to manage the
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// list. when it is non-zero the signal in known to be inactive
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std::map<int, int> known_inactive;
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// database of known active signals
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// the 2nd dimension is the list of or-ed signals. so we know that
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// for each i there is a j so that known_active[i][j] points to an
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// inactive control signal.
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std::vector<std::vector<int>> known_active;
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// this is just used to keep track of visited muxes in order to prohibit
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// endless recursion in mux loops
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std::set<int> visited_muxes;
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};
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void eval_mux_port(knowledge_t &knowledge, int mux_idx, int port_idx)
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{
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muxinfo_t &muxinfo = mux2info[mux_idx];
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muxinfo.ports[port_idx].enabled = true;
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for (size_t i = 0; i < muxinfo.ports.size(); i++) {
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if (int(i) == port_idx)
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continue;
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for (int b : muxinfo.ports[i].ctrl_sigs)
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knowledge.known_inactive[b]++;
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}
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if (port_idx < int(muxinfo.ports.size())-1 && !muxinfo.ports[port_idx].const_activated)
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knowledge.known_active.push_back(muxinfo.ports[port_idx].ctrl_sigs);
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for (int m : muxinfo.ports[port_idx].input_muxes) {
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if (knowledge.visited_muxes.count(m) > 0)
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continue;
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knowledge.visited_muxes.insert(m);
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eval_mux(knowledge, m);
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knowledge.visited_muxes.erase(m);
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}
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if (port_idx < int(muxinfo.ports.size())-1 && !muxinfo.ports[port_idx].const_activated)
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knowledge.known_active.pop_back();
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for (size_t i = 0; i < muxinfo.ports.size(); i++) {
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if (int(i) == port_idx)
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continue;
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for (int b : muxinfo.ports[i].ctrl_sigs)
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knowledge.known_inactive[b]--;
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}
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}
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void eval_mux(knowledge_t &knowledge, int mux_idx)
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{
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muxinfo_t &muxinfo = mux2info[mux_idx];
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// if there is a constant activated port we just use it
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for (size_t port_idx = 0; port_idx < muxinfo.ports.size()-1; port_idx++)
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{
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portinfo_t &portinfo = muxinfo.ports[port_idx];
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if (portinfo.const_activated) {
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eval_mux_port(knowledge, mux_idx, port_idx);
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return;
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}
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}
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// compare ports with known_active signals. if we find a match, only this
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// port can be active. do not include the last port (its the default port
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// that has no control signals).
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for (size_t port_idx = 0; port_idx < muxinfo.ports.size()-1; port_idx++)
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{
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portinfo_t &portinfo = muxinfo.ports[port_idx];
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for (size_t i = 0; i < knowledge.known_active.size(); i++) {
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if (list_is_subset(knowledge.known_active[i], portinfo.ctrl_sigs)) {
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eval_mux_port(knowledge, mux_idx, port_idx);
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return;
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}
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}
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}
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// compare ports with known_inactive and known_active signals. If all control
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// signals of the port are know_inactive or if the control signals of all other
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// ports are known_active this port can't be activated. this loop includes the
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// default port but no known_inactive match is performed on the default port.
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for (size_t port_idx = 0; port_idx < muxinfo.ports.size(); port_idx++)
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{
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portinfo_t &portinfo = muxinfo.ports[port_idx];
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if (port_idx < muxinfo.ports.size()-1) {
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bool found_non_known_inactive = false;
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for (int i : portinfo.ctrl_sigs)
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if (knowledge.known_inactive[i] == 0)
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found_non_known_inactive = true;
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if (!found_non_known_inactive)
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continue;
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}
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bool port_active = true;
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std::vector<int> other_ctrl_sig;
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for (size_t i = 0; i < muxinfo.ports.size()-1; i++) {
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if (i == port_idx)
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continue;
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other_ctrl_sig.insert(other_ctrl_sig.end(),
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muxinfo.ports[i].ctrl_sigs.begin(), muxinfo.ports[i].ctrl_sigs.end());
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}
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for (size_t i = 0; i < knowledge.known_active.size(); i++) {
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if (list_is_subset(knowledge.known_active[i], other_ctrl_sig))
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port_active = false;
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}
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if (port_active)
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eval_mux_port(knowledge, mux_idx, port_idx);
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}
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}
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void eval_root_mux(int mux_idx)
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{
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knowledge_t knowledge;
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eval_mux(knowledge, mux_idx);
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}
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};
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struct OptMuxtreePass : public Pass {
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OptMuxtreePass() : Pass("opt_muxtree", "eliminate dead trees in multiplexer trees") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_muxtree [selection]\n");
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log("\n");
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log("This pass analyzes the control signals for the multiplexer trees in the design\n");
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log("and identifies inputs that can never be active. It then removes this dead\n");
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log("branches from the multiplexer trees.\n");
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log("\n");
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log("This pass only operates on completely selected modules without processes.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
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extra_args(args, 1, design);
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int total_count = 0;
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for (auto &mod_it : design->modules) {
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if (!design->selected_whole_module(mod_it.first)) {
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if (design->selected(mod_it.second))
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log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name));
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continue;
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}
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if (mod_it.second->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", id2cstr(mod_it.second->name));
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} else {
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OptMuxtreeWorker worker(design, mod_it.second);
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total_count += worker.removed_count;
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}
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}
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log("Removed %d multiplexer ports.\n", total_count);
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}
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} OptMuxtreePass;
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