mirror of https://github.com/YosysHQ/yosys.git
736 lines
26 KiB
C++
736 lines
26 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/rtlil.h"
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#include "kernel/satgen.h"
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#include "kernel/sigtools.h"
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#include "kernel/modwalker.h"
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <algorithm>
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static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
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{
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if (a->type == "$memrd" && b->type == "$memrd")
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return a->name < b->name;
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if (a->type == "$memrd" || b->type == "$memrd")
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return (a->type == "$memrd") < (b->type == "$memrd");
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return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int();
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}
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struct MemoryShareWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap sigmap, sigmap_xmux;
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ModWalker modwalker;
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CellTypes cone_ct;
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std::map<RTLIL::SigBit, std::pair<RTLIL::Cell*, int>> sig_to_mux;
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std::map<std::set<std::map<RTLIL::SigBit, bool>>, RTLIL::SigBit> conditions_logic_cache;
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// -----------------------------------------------------------------
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// Converting feedbacks to async read ports to proper enable signals
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// -----------------------------------------------------------------
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bool find_data_feedback(const std::set<RTLIL::SigBit> &async_rd_bits, RTLIL::SigBit sig,
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std::map<RTLIL::SigBit, bool> &state, std::set<std::map<RTLIL::SigBit, bool>> &conditions)
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{
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if (async_rd_bits.count(sig)) {
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conditions.insert(state);
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return true;
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}
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if (sig_to_mux.count(sig) == 0)
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return false;
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RTLIL::Cell *cell = sig_to_mux.at(sig).first;
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int bit_idx = sig_to_mux.at(sig).second;
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std::vector<RTLIL::SigBit> sig_a = sigmap(cell->connections.at("\\A"));
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std::vector<RTLIL::SigBit> sig_b = sigmap(cell->connections.at("\\B"));
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std::vector<RTLIL::SigBit> sig_s = sigmap(cell->connections.at("\\S"));
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std::vector<RTLIL::SigBit> sig_y = sigmap(cell->connections.at("\\Y"));
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log_assert(sig_y.at(bit_idx) == sig);
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for (int i = 0; i < int(sig_s.size()); i++)
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if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) {
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if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions))
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cell->connections.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
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return false;
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}
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for (int i = 0; i < int(sig_s.size()); i++)
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{
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if (state.count(sig_s[i]) && state.at(sig_s[i]) == false)
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continue;
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std::map<RTLIL::SigBit, bool> new_state = state;
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new_state[sig_s[i]] = true;
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if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions))
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cell->connections.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
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}
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std::map<RTLIL::SigBit, bool> new_state = state;
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for (int i = 0; i < int(sig_s.size()); i++)
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new_state[sig_s[i]] = false;
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if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions))
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cell->connections.at("\\A").replace(bit_idx, RTLIL::State::Sx);
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return false;
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}
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RTLIL::SigBit conditions_to_logic(std::set<std::map<RTLIL::SigBit, bool>> &conditions, int &created_conditions)
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{
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if (conditions_logic_cache.count(conditions))
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return conditions_logic_cache.at(conditions);
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RTLIL::SigSpec terms;
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for (auto &cond : conditions) {
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RTLIL::SigSpec sig1, sig2;
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for (auto &it : cond) {
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sig1.append_bit(it.first);
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sig2.append_bit(it.second ? RTLIL::State::S1 : RTLIL::State::S0);
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}
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terms.append(module->Ne(NEW_ID, sig1, sig2));
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created_conditions++;
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}
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if (terms.size() > 1)
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terms = module->ReduceAnd(NEW_ID, terms);
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return conditions_logic_cache[conditions] = terms;
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}
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void translate_rd_feedback_to_en(std::string memid, std::vector<RTLIL::Cell*> &rd_ports, std::vector<RTLIL::Cell*> &wr_ports)
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{
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std::map<RTLIL::SigSpec, std::vector<std::set<RTLIL::SigBit>>> async_rd_bits;
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std::map<RTLIL::SigBit, std::set<RTLIL::SigBit>> muxtree_upstream_map;
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std::set<RTLIL::SigBit> non_feedback_nets;
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for (auto wire_it : module->wires)
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if (wire_it.second->port_output) {
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std::vector<RTLIL::SigBit> bits = RTLIL::SigSpec(wire_it.second);
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non_feedback_nets.insert(bits.begin(), bits.end());
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}
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for (auto cell_it : module->cells)
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{
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RTLIL::Cell *cell = cell_it.second;
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bool ignore_data_port = false;
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if (cell->type == "$mux" || cell->type == "$pmux")
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{
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std::vector<RTLIL::SigBit> sig_a = sigmap(cell->connections.at("\\A"));
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std::vector<RTLIL::SigBit> sig_b = sigmap(cell->connections.at("\\B"));
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std::vector<RTLIL::SigBit> sig_s = sigmap(cell->connections.at("\\S"));
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std::vector<RTLIL::SigBit> sig_y = sigmap(cell->connections.at("\\Y"));
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non_feedback_nets.insert(sig_s.begin(), sig_s.end());
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for (int i = 0; i < int(sig_y.size()); i++) {
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muxtree_upstream_map[sig_y[i]].insert(sig_a[i]);
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for (int j = 0; j < int(sig_s.size()); j++)
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muxtree_upstream_map[sig_y[i]].insert(sig_b[i + j*sig_y.size()]);
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}
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continue;
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}
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if ((cell->type == "$memwr" || cell->type == "$memrd") &&
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cell->parameters.at("\\MEMID").decode_string() == memid)
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ignore_data_port = true;
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for (auto conn : cell_it.second->connections)
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{
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if (ignore_data_port && conn.first == "\\DATA")
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continue;
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std::vector<RTLIL::SigBit> bits = sigmap(conn.second);
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non_feedback_nets.insert(bits.begin(), bits.end());
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}
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}
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std::set<RTLIL::SigBit> expand_non_feedback_nets = non_feedback_nets;
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while (!expand_non_feedback_nets.empty())
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{
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std::set<RTLIL::SigBit> new_expand_non_feedback_nets;
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for (auto &bit : expand_non_feedback_nets)
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if (muxtree_upstream_map.count(bit))
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for (auto &new_bit : muxtree_upstream_map.at(bit))
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if (!non_feedback_nets.count(new_bit)) {
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non_feedback_nets.insert(new_bit);
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new_expand_non_feedback_nets.insert(new_bit);
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}
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expand_non_feedback_nets.swap(new_expand_non_feedback_nets);
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}
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for (auto cell : rd_ports)
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{
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if (cell->parameters.at("\\CLK_ENABLE").as_bool())
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continue;
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RTLIL::SigSpec sig_addr = sigmap(cell->connections.at("\\ADDR"));
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std::vector<RTLIL::SigBit> sig_data = sigmap(cell->connections.at("\\DATA"));
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for (int i = 0; i < int(sig_data.size()); i++)
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if (non_feedback_nets.count(sig_data[i]))
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goto not_pure_feedback_port;
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async_rd_bits[sig_addr].resize(std::max(async_rd_bits.size(), sig_data.size()));
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for (int i = 0; i < int(sig_data.size()); i++)
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async_rd_bits[sig_addr][i].insert(sig_data[i]);
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not_pure_feedback_port:;
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}
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if (async_rd_bits.empty())
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return;
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log("Populating enable bits on write ports of memory %s.%s with aync read feedback:\n", log_id(module), log_id(memid));
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for (auto cell : wr_ports)
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{
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RTLIL::SigSpec sig_addr = sigmap_xmux(cell->connections.at("\\ADDR"));
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if (!async_rd_bits.count(sig_addr))
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continue;
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log(" Analyzing write port %s.\n", log_id(cell));
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std::vector<RTLIL::SigBit> cell_data = cell->connections.at("\\DATA");
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std::vector<RTLIL::SigBit> cell_en = cell->connections.at("\\EN");
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int created_conditions = 0;
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for (int i = 0; i < int(cell_data.size()); i++)
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if (cell_en[i] != RTLIL::SigBit(RTLIL::State::S0))
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{
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std::map<RTLIL::SigBit, bool> state;
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std::set<std::map<RTLIL::SigBit, bool>> conditions;
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if (cell_en[i].wire != NULL) {
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state[cell_en[i]] = false;
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conditions.insert(state);
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}
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find_data_feedback(async_rd_bits.at(sig_addr).at(i), cell_data[i], state, conditions);
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cell_en[i] = conditions_to_logic(conditions, created_conditions);
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}
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if (created_conditions) {
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log(" Added enable logic for %d different cases.\n", created_conditions);
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cell->connections.at("\\EN") = cell_en;
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}
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}
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}
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// ------------------------------------------------------
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// Consolidate write ports that write to the same address
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// ------------------------------------------------------
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RTLIL::SigSpec mask_en_naive(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits)
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{
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// this is the naive version of the function that does not care about grouping the EN bits.
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RTLIL::SigSpec inv_mask_bits = module->Not(NEW_ID, mask_bits);
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RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.size()), inv_mask_bits, do_mask);
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RTLIL::SigSpec result = module->And(NEW_ID, inv_mask_bits_filtered, bits);
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return result;
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}
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RTLIL::SigSpec mask_en_grouped(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits)
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{
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// this version of the function preserves the bit grouping in the EN bits.
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std::vector<RTLIL::SigBit> v_bits = bits;
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std::vector<RTLIL::SigBit> v_mask_bits = mask_bits;
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std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, std::pair<int, std::vector<int>>> groups;
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RTLIL::SigSpec grouped_bits, grouped_mask_bits;
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for (int i = 0; i < bits.size(); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
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if (groups.count(key) == 0) {
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groups[key].first = grouped_bits.size();
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grouped_bits.append_bit(v_bits[i]);
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grouped_mask_bits.append_bit(v_mask_bits[i]);
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}
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groups[key].second.push_back(i);
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}
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std::vector<RTLIL::SigBit> grouped_result = mask_en_naive(do_mask, grouped_bits, grouped_mask_bits);
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RTLIL::SigSpec result;
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for (int i = 0; i < bits.size(); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
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result.append_bit(grouped_result.at(groups.at(key).first));
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}
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return result;
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}
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void merge_en_data(RTLIL::SigSpec &merged_en, RTLIL::SigSpec &merged_data, RTLIL::SigSpec next_en, RTLIL::SigSpec next_data)
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{
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std::vector<RTLIL::SigBit> v_old_en = merged_en;
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std::vector<RTLIL::SigBit> v_next_en = next_en;
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// The new merged_en signal is just the old merged_en signal and next_en OR'ed together.
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// But of course we need to preserve the bit grouping..
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std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups;
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std::vector<RTLIL::SigBit> grouped_old_en, grouped_next_en;
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RTLIL::SigSpec new_merged_en;
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for (int i = 0; i < int(v_old_en.size()); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]);
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if (groups.count(key) == 0) {
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groups[key] = grouped_old_en.size();
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grouped_old_en.push_back(key.first);
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grouped_next_en.push_back(key.second);
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}
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}
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std::vector<RTLIL::SigBit> grouped_new_en = module->Or(NEW_ID, grouped_old_en, grouped_next_en);
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for (int i = 0; i < int(v_old_en.size()); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]);
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new_merged_en.append_bit(grouped_new_en.at(groups.at(key)));
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}
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// Create the new merged_data signal.
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RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.size());
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RTLIL::SigSpec old_data_set = module->And(NEW_ID, merged_en, merged_data);
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RTLIL::SigSpec old_data_unset = module->And(NEW_ID, merged_en, module->Not(NEW_ID, merged_data));
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RTLIL::SigSpec new_data_set = module->And(NEW_ID, next_en, next_data);
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RTLIL::SigSpec new_data_unset = module->And(NEW_ID, next_en, module->Not(NEW_ID, next_data));
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new_merged_data = module->Or(NEW_ID, new_merged_data, old_data_set);
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new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, old_data_unset));
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new_merged_data = module->Or(NEW_ID, new_merged_data, new_data_set);
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new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, new_data_unset));
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// Update merged_* signals
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merged_en = new_merged_en;
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merged_data = new_merged_data;
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}
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void consolidate_wr_by_addr(std::string memid, std::vector<RTLIL::Cell*> &wr_ports)
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{
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if (wr_ports.size() <= 1)
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return;
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log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(memid));
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std::map<RTLIL::SigSpec, int> last_port_by_addr;
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std::vector<std::vector<bool>> active_bits_on_port;
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bool cache_clk_enable = false;
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bool cache_clk_polarity = false;
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RTLIL::SigSpec cache_clk;
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for (int i = 0; i < int(wr_ports.size()); i++)
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{
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RTLIL::Cell *cell = wr_ports.at(i);
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RTLIL::SigSpec addr = sigmap_xmux(cell->connections.at("\\ADDR"));
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if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
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(cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk ||
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cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
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{
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cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
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cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
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cache_clk = sigmap(cell->connections.at("\\CLK"));
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last_port_by_addr.clear();
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if (cache_clk_enable)
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log(" New clock domain: %s %s\n", cache_clk_polarity ? "posedge" : "negedge", log_signal(cache_clk));
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else
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log(" New clock domain: unclocked\n");
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}
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log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr));
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log(" Active bits: ");
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std::vector<RTLIL::SigBit> en_bits = sigmap(cell->connections.at("\\EN"));
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active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
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for (int k = int(en_bits.size())-1; k >= 0; k--) {
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active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0;
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log("%c", active_bits_on_port[i][k] ? '1' : '0');
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}
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log("\n");
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if (last_port_by_addr.count(addr))
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{
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int last_i = last_port_by_addr.at(addr);
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log(" Merging port %d into this one.\n", last_i);
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bool found_overlapping_bits = false;
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for (int k = 0; k < int(en_bits.size()); k++) {
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if (active_bits_on_port[i][k] && active_bits_on_port[last_i][k])
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found_overlapping_bits = true;
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active_bits_on_port[i][k] = active_bits_on_port[i][k] || active_bits_on_port[last_i][k];
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}
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// Force this ports addr input to addr directly (skip don't care muxes)
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cell->connections.at("\\ADDR") = addr;
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// If any of the ports between `last_i' and `i' write to the same address, this
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// will have priority over whatever `last_i` wrote. So we need to revisit those
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// ports and mask the EN bits accordingly.
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RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->connections.at("\\EN"));
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for (int j = last_i+1; j < i; j++)
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{
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if (wr_ports[j] == NULL)
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continue;
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for (int k = 0; k < int(en_bits.size()); k++)
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if (active_bits_on_port[i][k] && active_bits_on_port[j][k])
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goto found_overlapping_bits_i_j;
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if (0) {
|
|
found_overlapping_bits_i_j:
|
|
log(" Creating collosion-detect logic for port %d.\n", j);
|
|
RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
|
|
module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr);
|
|
merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN")));
|
|
}
|
|
}
|
|
|
|
// Then we need to merge the (masked) EN and the DATA signals.
|
|
|
|
RTLIL::SigSpec merged_data = wr_ports[last_i]->connections.at("\\DATA");
|
|
if (found_overlapping_bits) {
|
|
log(" Creating logic for merging DATA and EN ports.\n");
|
|
merge_en_data(merged_en, merged_data, sigmap(cell->connections.at("\\EN")), sigmap(cell->connections.at("\\DATA")));
|
|
} else {
|
|
RTLIL::SigSpec cell_en = sigmap(cell->connections.at("\\EN"));
|
|
RTLIL::SigSpec cell_data = sigmap(cell->connections.at("\\DATA"));
|
|
for (int k = 0; k < int(en_bits.size()); k++)
|
|
if (!active_bits_on_port[last_i][k]) {
|
|
merged_en.replace(k, cell_en.extract(k, 1));
|
|
merged_data.replace(k, cell_data.extract(k, 1));
|
|
}
|
|
}
|
|
|
|
// Connect the new EN and DATA signals and remove the old write port.
|
|
|
|
cell->connections.at("\\EN") = merged_en;
|
|
cell->connections.at("\\DATA") = merged_data;
|
|
|
|
module->cells.erase(wr_ports[last_i]->name);
|
|
delete wr_ports[last_i];
|
|
wr_ports[last_i] = NULL;
|
|
|
|
log(" Active bits: ");
|
|
std::vector<RTLIL::SigBit> en_bits = sigmap(cell->connections.at("\\EN"));
|
|
active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
|
|
for (int k = int(en_bits.size())-1; k >= 0; k--)
|
|
log("%c", active_bits_on_port[i][k] ? '1' : '0');
|
|
log("\n");
|
|
}
|
|
|
|
last_port_by_addr[addr] = i;
|
|
}
|
|
|
|
// Clean up `wr_ports': remove all NULL entries
|
|
|
|
std::vector<RTLIL::Cell*> wr_ports_with_nulls;
|
|
wr_ports_with_nulls.swap(wr_ports);
|
|
|
|
for (auto cell : wr_ports_with_nulls)
|
|
if (cell != NULL)
|
|
wr_ports.push_back(cell);
|
|
}
|
|
|
|
|
|
// --------------------------------------------------------
|
|
// Consolidate write ports using sat-based resource sharing
|
|
// --------------------------------------------------------
|
|
|
|
void consolidate_wr_using_sat(std::string memid, std::vector<RTLIL::Cell*> &wr_ports)
|
|
{
|
|
if (wr_ports.size() <= 1)
|
|
return;
|
|
|
|
ezDefaultSAT ez;
|
|
SatGen satgen(&ez, &modwalker.sigmap);
|
|
|
|
// find list of considered ports and port pairs
|
|
|
|
std::set<int> considered_ports;
|
|
std::set<int> considered_port_pairs;
|
|
|
|
for (int i = 0; i < int(wr_ports.size()); i++) {
|
|
std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->connections.at("\\EN"));
|
|
for (auto bit : bits)
|
|
if (bit == RTLIL::State::S1)
|
|
goto port_is_always_active;
|
|
if (modwalker.has_drivers(bits))
|
|
considered_ports.insert(i);
|
|
port_is_always_active:;
|
|
}
|
|
|
|
log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", log_id(module), log_id(memid));
|
|
|
|
bool cache_clk_enable = false;
|
|
bool cache_clk_polarity = false;
|
|
RTLIL::SigSpec cache_clk;
|
|
|
|
for (int i = 0; i < int(wr_ports.size()); i++)
|
|
{
|
|
RTLIL::Cell *cell = wr_ports.at(i);
|
|
|
|
if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
|
|
(cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk ||
|
|
cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
|
|
{
|
|
cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
|
|
cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
|
|
cache_clk = sigmap(cell->connections.at("\\CLK"));
|
|
}
|
|
else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i))
|
|
considered_port_pairs.insert(i);
|
|
|
|
if (cache_clk_enable)
|
|
log(" Port %d (%s) on %s %s: %s\n", i, log_id(cell),
|
|
cache_clk_polarity ? "posedge" : "negedge", log_signal(cache_clk),
|
|
considered_ports.count(i) ? "considered" : "not considered");
|
|
else
|
|
log(" Port %d (%s) unclocked: %s\n", i, log_id(cell),
|
|
considered_ports.count(i) ? "considered" : "not considered");
|
|
}
|
|
|
|
if (considered_port_pairs.size() < 1) {
|
|
log(" No two subsequent ports in same clock domain considered -> nothing to consolidate.\n");
|
|
return;
|
|
}
|
|
|
|
// create SAT representation of common input cone of all considered EN signals
|
|
|
|
std::set<RTLIL::Cell*> sat_cells;
|
|
std::set<RTLIL::SigBit> bits_queue;
|
|
std::map<int, int> port_to_sat_variable;
|
|
|
|
for (int i = 0; i < int(wr_ports.size()); i++)
|
|
if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1))
|
|
{
|
|
RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->connections.at("\\EN"));
|
|
port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig));
|
|
|
|
std::vector<RTLIL::SigBit> bits = sig;
|
|
bits_queue.insert(bits.begin(), bits.end());
|
|
}
|
|
|
|
while (!bits_queue.empty())
|
|
{
|
|
std::set<ModWalker::PortBit> portbits;
|
|
modwalker.get_drivers(portbits, bits_queue);
|
|
bits_queue.clear();
|
|
|
|
for (auto &pbit : portbits)
|
|
if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) {
|
|
std::set<RTLIL::SigBit> &cell_inputs = modwalker.cell_inputs[pbit.cell];
|
|
bits_queue.insert(cell_inputs.begin(), cell_inputs.end());
|
|
sat_cells.insert(pbit.cell);
|
|
}
|
|
}
|
|
|
|
log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size()));
|
|
|
|
for (auto cell : sat_cells)
|
|
satgen.importCell(cell);
|
|
|
|
log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", ez.numCnfVariables(), ez.numCnfClauses());
|
|
|
|
// merge subsequent ports if possible
|
|
|
|
for (int i = 0; i < int(wr_ports.size()); i++)
|
|
{
|
|
if (!considered_port_pairs.count(i))
|
|
continue;
|
|
|
|
if (ez.solve(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i))) {
|
|
log(" According to SAT solver sharing of port %d with port %d is not possible.\n", i-1, i);
|
|
continue;
|
|
}
|
|
|
|
log(" Merging port %d into port %d.\n", i-1, i);
|
|
port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
|
|
|
|
RTLIL::SigSpec last_addr = wr_ports[i-1]->connections.at("\\ADDR");
|
|
RTLIL::SigSpec last_data = wr_ports[i-1]->connections.at("\\DATA");
|
|
std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->connections.at("\\EN"));
|
|
|
|
RTLIL::SigSpec this_addr = wr_ports[i]->connections.at("\\ADDR");
|
|
RTLIL::SigSpec this_data = wr_ports[i]->connections.at("\\DATA");
|
|
std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->connections.at("\\EN"));
|
|
|
|
RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
|
|
|
|
wr_ports[i]->connections.at("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
|
|
wr_ports[i]->connections.at("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active);
|
|
|
|
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
|
|
RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
|
|
RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
|
|
|
|
for (int j = 0; j < int(this_en.size()); j++) {
|
|
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
|
|
if (!groups_en.count(key)) {
|
|
grouped_last_en.append_bit(last_en[j]);
|
|
grouped_this_en.append_bit(this_en[j]);
|
|
groups_en[key] = grouped_en->width;
|
|
grouped_en->width++;
|
|
}
|
|
en.append(RTLIL::SigSpec(grouped_en, groups_en[key]));
|
|
}
|
|
|
|
module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
|
|
wr_ports[i]->connections.at("\\EN") = en;
|
|
|
|
module->cells.erase(wr_ports[i-1]->name);
|
|
delete wr_ports[i-1];
|
|
wr_ports[i-1] = NULL;
|
|
}
|
|
|
|
// Clean up `wr_ports': remove all NULL entries
|
|
|
|
std::vector<RTLIL::Cell*> wr_ports_with_nulls;
|
|
wr_ports_with_nulls.swap(wr_ports);
|
|
|
|
for (auto cell : wr_ports_with_nulls)
|
|
if (cell != NULL)
|
|
wr_ports.push_back(cell);
|
|
}
|
|
|
|
|
|
// -------------
|
|
// Setup and run
|
|
// -------------
|
|
|
|
MemoryShareWorker(RTLIL::Design *design, RTLIL::Module *module) :
|
|
design(design), module(module), sigmap(module)
|
|
{
|
|
std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
|
|
|
|
sigmap_xmux = sigmap;
|
|
for (auto &it : module->cells)
|
|
{
|
|
RTLIL::Cell *cell = it.second;
|
|
|
|
if (cell->type == "$memrd")
|
|
memindex[cell->parameters.at("\\MEMID").decode_string()].first.push_back(cell);
|
|
|
|
if (cell->type == "$memwr")
|
|
memindex[cell->parameters.at("\\MEMID").decode_string()].second.push_back(cell);
|
|
|
|
if (cell->type == "$mux")
|
|
{
|
|
RTLIL::SigSpec sig_a = sigmap_xmux(cell->connections.at("\\A"));
|
|
RTLIL::SigSpec sig_b = sigmap_xmux(cell->connections.at("\\B"));
|
|
|
|
if (sig_a.is_fully_undef())
|
|
sigmap_xmux.add(cell->connections.at("\\Y"), sig_b);
|
|
else if (sig_b.is_fully_undef())
|
|
sigmap_xmux.add(cell->connections.at("\\Y"), sig_a);
|
|
}
|
|
|
|
if (cell->type == "$mux" || cell->type == "$pmux")
|
|
{
|
|
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->connections.at("\\Y"));
|
|
for (int i = 0; i < int(sig_y.size()); i++)
|
|
sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i);
|
|
}
|
|
}
|
|
|
|
for (auto &it : memindex) {
|
|
std::sort(it.second.first.begin(), it.second.first.end(), memcells_cmp);
|
|
std::sort(it.second.second.begin(), it.second.second.end(), memcells_cmp);
|
|
translate_rd_feedback_to_en(it.first, it.second.first, it.second.second);
|
|
consolidate_wr_by_addr(it.first, it.second.second);
|
|
}
|
|
|
|
cone_ct.setup_internals();
|
|
cone_ct.cell_types.erase("$mul");
|
|
cone_ct.cell_types.erase("$mod");
|
|
cone_ct.cell_types.erase("$div");
|
|
cone_ct.cell_types.erase("$pow");
|
|
cone_ct.cell_types.erase("$shl");
|
|
cone_ct.cell_types.erase("$shr");
|
|
cone_ct.cell_types.erase("$sshl");
|
|
cone_ct.cell_types.erase("$sshr");
|
|
|
|
modwalker.setup(design, module, &cone_ct);
|
|
|
|
for (auto &it : memindex)
|
|
consolidate_wr_using_sat(it.first, it.second.second);
|
|
}
|
|
};
|
|
|
|
struct MemorySharePass : public Pass {
|
|
MemorySharePass() : Pass("memory_share", "consolidate memory ports") { }
|
|
virtual void help()
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" memory_share [selection]\n");
|
|
log("\n");
|
|
log("This pass merges share-able memory ports into single memory ports.\n");
|
|
log("\n");
|
|
log("The following methods are used to consolidate the number of memory ports:\n");
|
|
log("\n");
|
|
log(" - When write ports are connected to async read ports accessing the same\n");
|
|
log(" address, then this feedback path is converted to a write port with\n");
|
|
log(" byte/part enable signals.\n");
|
|
log("\n");
|
|
log(" - When multiple write ports access the same adress then this is converted\n");
|
|
log(" to a single write port with a more complex data and/or enable logic path.\n");
|
|
log("\n");
|
|
log(" - When multiple write ports are never accessed at the same time (a SAT\n");
|
|
log(" solver is used to determine this), then the ports are merged into a single\n");
|
|
log(" write port.\n");
|
|
log("\n");
|
|
log("Note that in addition to the algorithms implemented in this pass, the $memrd\n");
|
|
log("and $memwr cells are also subject to generic resource sharing passes (and other\n");
|
|
log("optimizations) such as opt_share.\n");
|
|
log("\n");
|
|
}
|
|
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
|
|
log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n");
|
|
extra_args(args, 1, design);
|
|
for (auto &mod_it : design->modules)
|
|
if (design->selected(mod_it.second))
|
|
MemoryShareWorker(design, mod_it.second);
|
|
}
|
|
} MemorySharePass;
|
|
|