Clifford Wolf 58238da133 Progress in shiftmul peepopt pattern ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2019-04-30 07:59:39 +02:00
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cmds	Add log_debug() framework	2019-04-22 17:25:52 +02:00
equiv	Add "techmap -wb", use in formal flows	2019-04-20 11:23:24 +02:00
fsm	fsm_opt: Fix runtime error for FSMs without a reset state	2019-02-07 10:35:36 +00:00
hierarchy	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00
memory	memory_bram: Fix multiport make_transp	2019-04-07 16:56:31 +01:00
opt	Remove some left-over log_dump()	2019-04-23 17:55:41 +02:00
pmgen	Progress in shiftmul peepopt pattern	2019-04-30 07:59:39 +02:00
proc	Improve proc full_case detection and handling, fixes #931	2019-04-18 15:13:47 +02:00
sat	Add "techmap -wb", use in formal flows	2019-04-20 11:23:24 +02:00
techmap	Merge pull request #914 from YosysHQ/xc7srl	2019-04-22 13:31:30 -07:00
tests	flowmap: implement depth relaxation.	2019-01-08 01:13:05 +00:00