mirror of https://github.com/YosysHQ/yosys.git
41 lines
937 B
Verilog
41 lines
937 B
Verilog
module xilinx_srl_static_test(input i, clk, output [1:0] q);
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reg head = 1'b0;
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reg [3:0] shift1 = 4'b0000;
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reg [3:0] shift2 = 4'b0000;
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always @(posedge clk) begin
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head <= i;
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shift1 <= {shift1[2:0], head};
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shift2 <= {shift2[2:0], head};
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end
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assign q = {shift2[3], shift1[3]};
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endmodule
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module xilinx_srl_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q);
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reg head = 1'b0;
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reg [3:0] shift1 = 4'b0000;
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reg [3:0] shift2 = 4'b0000;
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always @(posedge clk) begin
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head <= i;
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shift1 <= {shift1[2:0], head};
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shift2 <= {shift2[2:0], head};
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end
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assign q = {shift2[l2], shift1[l1]};
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endmodule
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module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
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parameter CLKPOL = 1;
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parameter ENPOL = 1;
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parameter DEPTH = 1;
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parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
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reg [DEPTH-1:0] r = INIT;
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wire clk = C ^ CLKPOL;
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always @(posedge C)
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if (E)
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r <= { r[DEPTH-2:0], D };
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assign Q = r[L];
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endmodule
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