mirror of https://github.com/YosysHQ/yosys.git
48 lines
768 B
Verilog
48 lines
768 B
Verilog
module adff
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( input d, clk, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, posedge clr )
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if ( clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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module adffn
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( input d, clk, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, negedge clr )
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if ( !clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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module dffs
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( input d, clk, pre, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk )
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if ( pre )
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q <= 1'b1;
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else
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q <= d;
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endmodule
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module ndffnr
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( input d, clk, pre, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( negedge clk )
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if ( !clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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