mirror of https://github.com/YosysHQ/yosys.git
53 lines
1.6 KiB
Plaintext
53 lines
1.6 KiB
Plaintext
read_verilog <<EOT
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module clkbuf (input i, (* clkbuf_driver *) output o); endmodule
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module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule
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module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule
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module latch (input e, d, output q); endmodule
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module top(input clk1, clk2, clk3, d, e, output [2:0] q);
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dff s0 (.clk(clk1), .d(d), .q(q[0]));
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dffe s1 (.c(clk2), .d(d), .e(e), .q(q[1]));
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latch s2 (.e(clk3), .d(d), .q(q[2]));
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endmodule
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EOT
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hierarchy -auto-top
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design -save ref
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# ----------------------
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design -load ref
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clkbufmap -buf clkbuf o:i
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select -assert-count 1 w:clk1 %a %co t:clkbuf %i
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select -assert-count 1 w:clk2 %a %co t:clkbuf %i
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select -assert-count 2 t:clkbuf
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# ----------------------
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design -load ref
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setattr -set clkbuf_inhibit 0 w:clk1
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setattr -set clkbuf_inhibit 1 w:clk2
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clkbufmap -buf clkbuf o:i
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select -assert-count 1 w:clk1 %a %co t:clkbuf %i
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select -assert-count 0 w:clk2 %a %co t:clkbuf %i
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select -assert-count 1 t:clkbuf
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# ----------------------
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design -load ref
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setattr -set buffer_type "bufg" w:clk2
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clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
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select -assert-count 1 w:clk1 %a %co t:clkbuf %i
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select -assert-count 1 w:clk2 %a %co t:clkbuf %i
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select -assert-count 2 t:clkbuf
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# ----------------------
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design -load ref
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setattr -set buffer_type "none" w:clk1
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setattr -set buffer_type "bufr" w:clk2
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clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
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select -assert-count 0 w:clk1 %a %co t:clkbuf %i
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select -assert-count 0 w:clk2 %a %co t:clkbuf %i
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select -assert-count 0 t:clkbuf
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