This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
55fbc1a355
yosys
/
manual
/
PRESENTATION_ExSyn
/
memory_01.ys
4 lines
71 B
Plaintext
Raw
Blame
History
read_verilog memory_01.v
hierarchy -check -top test
proc;; memory; opt
Reference in New Issue
View Git Blame
Copy Permalink