mirror of https://github.com/YosysHQ/yosys.git
38 lines
781 B
Verilog
38 lines
781 B
Verilog
(* techmap_celltype = "$lcu" *)
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module _80_lcu_sklansky (P, G, CI, CO);
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parameter WIDTH = 2;
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(* force_downto *)
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input [WIDTH-1:0] P, G;
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input CI;
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(* force_downto *)
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output [WIDTH-1:0] CO;
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integer i, j;
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(* force_downto *)
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reg [WIDTH-1:0] p, g;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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always @* begin
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p = P;
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g = G;
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// in almost all cases CI will be constant zero
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g[0] = g[0] | (p[0] & CI);
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for (i = 0; i < $clog2(WIDTH); i = i + 1) begin
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// iterate in reverse so we don't confuse a result from this stage and the previous
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for (j = WIDTH - 1; j >= 0; j = j - 1) begin
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if (j & 2**i) begin
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g[j] = g[j] | p[j] & g[(j & ~(2**i - 1)) - 1];
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p[j] = p[j] & p[(j & ~(2**i - 1)) - 1];
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end
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end
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end
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end
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assign CO = g;
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endmodule
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