This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
558f313a78
yosys
/
tests
/
techmap
/
recursive.v
9 lines
75 B
Verilog
Raw
Blame
History
module
top
;
sub
s0
(
)
;
foo
f0
(
)
;
endmodule
module
foo
;
sub
s0
(
)
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink