mirror of https://github.com/YosysHQ/yosys.git
42 lines
1.2 KiB
Verilog
42 lines
1.2 KiB
Verilog
module bram1 #(
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parameter ABITS = 8, DBITS = 8, TRANSP = 0
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) (
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input clk,
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input [ABITS-1:0] WR_ADDR,
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input [DBITS-1:0] WR_DATA,
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input WR_EN,
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input [ABITS-1:0] RD_ADDR,
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output [DBITS-1:0] RD_DATA
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);
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localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
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localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
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localparam [ABITS-1:0] INIT_ADDR_2 = 2**ABITS-1;
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localparam [ABITS-1:0] INIT_ADDR_3 = (2**ABITS-1) / 2;
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localparam [DBITS-1:0] INIT_DATA_0 = 128'h 51e152a7300e309ccb8cd06d34558f49;
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localparam [DBITS-1:0] INIT_DATA_1 = 128'h 07b1fe94a530ddf3027520f9d23ab43e;
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localparam [DBITS-1:0] INIT_DATA_2 = 128'h 3cedc6de43ef3f607af3193658d0eb0b;
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localparam [DBITS-1:0] INIT_DATA_3 = 128'h f6bc5514a8abf1e2810df966bcc13b46;
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reg [DBITS-1:0] memory [0:2**ABITS-1];
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reg [ABITS-1:0] RD_ADDR_BUF;
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reg [DBITS-1:0] RD_DATA_BUF;
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initial begin
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memory[INIT_ADDR_0] <= INIT_DATA_0;
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memory[INIT_ADDR_1] <= INIT_DATA_1;
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memory[INIT_ADDR_2] <= INIT_DATA_2;
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memory[INIT_ADDR_3] <= INIT_DATA_3;
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end
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always @(posedge clk) begin
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if (WR_EN) memory[WR_ADDR] <= WR_DATA;
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RD_ADDR_BUF <= RD_ADDR;
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RD_DATA_BUF <= memory[RD_ADDR];
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end
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assign RD_DATA = TRANSP ? memory[RD_ADDR_BUF] : RD_DATA_BUF;
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endmodule
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