mirror of https://github.com/YosysHQ/yosys.git
271 lines
7.3 KiB
Plaintext
271 lines
7.3 KiB
Plaintext
pattern fixed
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state <IdString> clk_port en_port
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udata <vector<Cell*>> chain longest_chain
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udata <pool<Cell*>> non_first_cells
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udata <int> minlen
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udata <dict<std::pair<IdString,IdString>,Const>> default_params
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code
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non_first_cells.clear();
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subpattern(setup);
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endcode
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match first
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select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
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select !first->has_keep_attr()
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filter !non_first_cells.count(first)
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//generate
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// SigSpec A = module->addWire(NEW_ID);
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// SigSpec B = module->addWire(NEW_ID);
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// SigSpec Y = module->addWire(NEW_ID);
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// switch (rng(3))
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// {
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// case 0:
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// module->addAndGate(NEW_ID, A, B, Y);
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// break;
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// case 1:
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// module->addOrGate(NEW_ID, A, B, Y);
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// break;
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// case 2:
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// module->addXorGate(NEW_ID, A, B, Y);
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// break;
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// }
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endmatch
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code clk_port en_port
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if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1))
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clk_port = \C;
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else log_abort();
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if (first->type.in($_DFF_N_, $_DFF_P_))
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en_port = IdString();
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else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
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en_port = \E;
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else if (first->type.in(\FDRE, \FDRE_1))
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en_port = \CE;
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else log_abort();
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longest_chain.clear();
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chain.push_back(first);
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subpattern(tail);
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finally
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chain.pop_back();
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log_assert(chain.empty());
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if (GetSize(longest_chain) >= minlen)
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accept;
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endcode
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// ------------------------------------------------------------------
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subpattern setup
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arg clk_port
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arg en_port
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match first
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select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
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select !first->has_keep_attr()
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endmatch
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code clk_port en_port
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if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1))
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clk_port = \C;
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else log_abort();
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if (first->type.in($_DFF_N_, $_DFF_P_))
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en_port = IdString();
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else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
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en_port = \E;
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else if (first->type.in(\FDRE, \FDRE_1))
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en_port = \CE;
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else log_abort();
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if (first->type.in(\FDRE, \FDRE_1)) {
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SigBit R = port(first, \R);
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if (first->type == \FDRE) {
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auto inverted = first->parameters.at(\IS_R_INVERTED, default_params.at(std::make_pair(first->type,\IS_R_INVERTED))).as_bool();
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if (!inverted && R != State::S0)
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reject;
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if (inverted && R != State::S1)
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reject;
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}
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else if (first->type == \FDRE_1) {
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if (R == State::S0)
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reject;
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}
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else log_abort();
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}
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endcode
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match next
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select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
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select !next->has_keep_attr()
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select !port(next, \D)[0].wire->get_bool_attribute(\keep)
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select nusers(port(next, \Q)) == 2
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index <IdString> next->type === first->type
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index <SigBit> port(next, \Q) === port(first, \D)
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filter port(next, clk_port) == port(first, clk_port)
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filter en_port == IdString() || port(next, en_port) == port(first, en_port)
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endmatch
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code
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if (next->type.in(\FDRE, \FDRE_1)) {
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for (auto p : { \R })
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if (port(next, p) != port(first, p))
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reject;
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if (next->type == \FDRE) {
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for (auto p : { \IS_C_INVERTED, \IS_D_INVERTED, \IS_R_INVERTED }) {
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auto n = next->parameters.at(p, default_params.at(std::make_pair(next->type,p)));
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auto f = first->parameters.at(p, default_params.at(std::make_pair(first->type,p)));
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if (n != f)
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reject;
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}
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}
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}
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non_first_cells.insert(next);
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endcode
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// ------------------------------------------------------------------
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subpattern tail
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arg first
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arg clk_port
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arg en_port
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match next
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semioptional
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select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
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select !next->has_keep_attr()
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select !port(next, \D)[0].wire->get_bool_attribute(\keep)
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select nusers(port(next, \Q)) == 2
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index <IdString> next->type === chain.back()->type
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index <SigBit> port(next, \Q) === port(chain.back(), \D)
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filter port(next, clk_port) == port(first, clk_port)
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filter en_port == IdString() || port(next, en_port) == port(first, en_port)
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//generate 10
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// SigSpec A = module->addWire(NEW_ID);
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// SigSpec B = module->addWire(NEW_ID);
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// SigSpec Y = port(chain.back().first, chain.back().second);
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// Cell *c = module->addAndGate(NEW_ID, A, B, Y);
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// c->type = chain.back().first->type;
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endmatch
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code
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if (next) {
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chain.push_back(next);
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if (next->type.in(\FDRE, \FDRE_1)) {
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for (auto p : { \R })
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if (port(next, p) != port(first, p))
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reject;
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if (next->type == \FDRE) {
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for (auto p : { \IS_C_INVERTED, \IS_D_INVERTED, \IS_R_INVERTED }) {
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auto n = next->parameters.at(p, default_params.at(std::make_pair(next->type,p)));
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auto f = first->parameters.at(p, default_params.at(std::make_pair(first->type,p)));
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if (n != f)
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reject;
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}
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}
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}
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subpattern(tail);
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} else {
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if (GetSize(chain) > GetSize(longest_chain))
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longest_chain = chain;
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}
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finally
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if (next)
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chain.pop_back();
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endcode
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// -----------
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pattern variable
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state <IdString> clk_port en_port
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state <int> shiftx_width
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state <int> slice
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udata <int> minlen
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udata <vector<pair<Cell*,int>>> chain
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udata <pool<SigBit>> chain_bits
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code
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chain_bits.clear();
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endcode
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match shiftx
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select shiftx->type.in($shiftx)
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select !shiftx->has_keep_attr()
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select param(shiftx, \Y_WIDTH).as_int() == 1
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filter param(shiftx, \A_WIDTH).as_int() >= minlen
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endmatch
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code shiftx_width
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shiftx_width = param(shiftx, \A_WIDTH).as_int();
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endcode
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match first
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select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
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select !first->has_keep_attr()
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slice idx GetSize(port(first, \Q))
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select nusers(port(first, \Q)[idx]) <= 2
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index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1]
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set slice idx
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endmatch
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code clk_port en_port
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if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
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clk_port = \C;
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else if (first->type.in($dff, $dffe))
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clk_port = \CLK;
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else log_abort();
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if (first->type.in($_DFF_N_, $_DFF_P_, $dff))
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en_port = IdString();
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else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
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en_port = \E;
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else if (first->type.in($dffe))
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en_port = \EN;
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else log_abort();
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chain.emplace_back(first, slice);
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subpattern(tail);
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finally
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if (GetSize(chain) == shiftx_width)
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accept;
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chain.clear();
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endcode
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// ------------------------------------------------------------------
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subpattern tail
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arg first
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arg shiftx
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arg shiftx_width
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arg slice
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arg clk_port
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arg en_port
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match next
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semioptional
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select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
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select !next->has_keep_attr()
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select !port(next, \D)[0].wire->get_bool_attribute(\keep)
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slice idx GetSize(port(next, \Q))
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select nusers(port(next, \Q)[idx]) <= 3
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index <IdString> next->type === chain.back().first->type
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index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second]
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index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
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filter port(next, clk_port) == port(first, clk_port)
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filter en_port == IdString() || port(next, en_port) == port(first, en_port)
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filter !chain_bits.count(port(next, \D)[idx])
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set slice idx
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endmatch
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code
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if (next) {
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chain_bits.insert(port(next, \Q)[slice]);
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chain.emplace_back(next, slice);
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if (GetSize(chain) < shiftx_width)
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subpattern(tail);
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}
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endcode
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