mirror of https://github.com/YosysHQ/yosys.git
95 lines
2.4 KiB
Plaintext
95 lines
2.4 KiB
Plaintext
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
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# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf
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# NB: Inputs/Outputs must be ordered alphabetically
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# (with exceptions for carry in/out)
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# Average across F7[AB]MUX
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# Inputs: I0 I1 S0
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# Outputs: O
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F7MUX 1 1 3 1
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204 208 286
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# Inputs: I0 I1 S0
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# Outputs: O
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MUXF8 2 1 3 1
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104 94 273
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# Box containing MUXF7.[AB] + MUXF8
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# Inputs: I0 I1 I2 I3 S0 S1
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# Outputs: O
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$__MUXF78 3 1 6 1
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294 297 311 317 390 273
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# CARRY4 + CARRY4_[ABCD]X
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# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
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# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
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# (NB: carry chain input/output must be last
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# input/output and the entire bus has been
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# moved there overriding the otherwise
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# alphabetical ordering)
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CARRY4 4 1 10 8
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482 - - - - 223 - - - 222
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598 407 - - - 400 205 - - 334
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584 556 537 - - 523 558 226 - 239
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642 615 596 438 - 582 618 330 227 313
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536 379 - - - 340 - - - 271
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494 465 445 - - 433 469 - - 157
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592 540 520 356 - 512 548 292 - 228
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580 526 507 398 385 508 528 378 380 114
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# Box to emulate async behaviour of FD[CP]*
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# Inputs: A S
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# Outputs: Y
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$__ABC_ASYNC 1000 0 2 1
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0 764
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# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
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# reflect the -46ps Tsu
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# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
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# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
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# Inputs: C CE D R \$pastQ
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# Outputs: Q
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FDRE 1001 1 5 1
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0 151 0 446 0
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# Inputs: C CE D R \$pastQ
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# Outputs: Q
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FDRE_1 1002 1 5 1
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0 151 0 446 0
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# Inputs: C CE CLR D \$pastQ
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# Outputs: Q
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FDCE 1003 1 5 1
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0 151 806 0 0
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# Inputs: C CE CLR D \$pastQ
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# Outputs: Q
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FDCE_1 1004 1 5 1
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0 151 806 0 0
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# Inputs: C CE D PRE \$pastQ
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# Outputs: Q
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FDPE 1005 1 5 1
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0 151 0 806 0
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# Inputs: C CE D PRE \$pastQ
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# Outputs: Q
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FDPE_1 1006 1 5 1
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0 151 0 806 0
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# SLICEM/A6LUT
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# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
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# Inputs: A S0 S1 S2 S3 S4 S5
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# Outputs: Y
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$__ABC_LUTRAM6 2000 0 7 1
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0 642 631 472 407 238 127
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# SLICEM/A6LUT + F7BMUX
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# Box to emulate comb/seq behaviour of RAMD128
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# Inputs: A S0 S1 S2 S3 S4 S5 S6
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# Outputs: DPO SPO
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$__ABC_LUTRAM7 2001 0 8 1
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0 1047 1036 877 812 643 532 478
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