yosys/frontends
Clifford Wolf 5387ccb041 Set Verific flag vhdl_support_variable_slice=1
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-09 21:03:23 +01:00
..
ast Various indenting fixes in AST front-end (mostly space vs tab issues) 2018-11-04 10:19:32 +01:00
blif Merge pull request #591 from hzeller/virtual-override 2018-08-15 14:05:38 +02:00
ilang Add "make coverage" 2018-08-27 14:22:21 +02:00
json Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
liberty Allow square brackets in liberty identifiers 2018-11-05 12:33:33 +01:00
verific Set Verific flag vhdl_support_variable_slice=1 2018-11-09 21:03:23 +01:00
verilog Add warning for SV "restrict" without "property" 2018-11-04 15:57:17 +01:00