mirror of https://github.com/YosysHQ/yosys.git
11 lines
348 B
Plaintext
11 lines
348 B
Plaintext
read_verilog -icells <<EOT
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module dlatchsr(input d, set, clr, en, output reg q);
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$dlatchsr #(.EN_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b1), .WIDTH(1)) uut (.EN(en), .SET(set), .CLR(clr), .D(d), .Q(q));
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endmodule
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EOT
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proc
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opt_dff
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stat
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select -assert-count 1 t:$dlatchsr
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sim -r tb_dlatchsr.fst -scope tb_dlatchsr.uut -sim-cmp dlatchsr
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