mirror of https://github.com/YosysHQ/yosys.git
25 lines
498 B
Verilog
25 lines
498 B
Verilog
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module demo_001(y1, y2, y3, y4);
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output [7:0] y1, y2, y3, y4;
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localparam [7:0] p1 = 123.45;
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localparam real p2 = 123.45;
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localparam real p3 = 123;
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localparam p4 = 123.45;
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assign y1 = p1 + 0.2;
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assign y2 = p2 + 0.2;
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assign y3 = p3 + 0.2;
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assign y4 = p4 + 0.2;
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endmodule
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module demo_002(y0, y1, y2, y3);
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output [63:0] y0, y1, y2, y3;
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assign y0 = 1'bx >= (-1 * -1.17);
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assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0;
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assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0;
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assign y3 = 1 ? -1 : 'd0;
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endmodule
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