mirror of https://github.com/YosysHQ/yosys.git
126 lines
3.7 KiB
Verilog
126 lines
3.7 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// SPI Slave Model ////
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//// ////
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//// ////
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//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws ////
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//// ////
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//// http://www.opencores.org/projects/simple_spi/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: spi_slave_model.v,v 1.1 2004-02-28 15:32:54 rherveille Exp $
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//
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// $Date: 2004-02-28 15:32:54 $
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// $Revision: 1.1 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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//
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//
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// Requires: Verilog2001
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`include "timescale.v"
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module spi_slave_model (
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input wire csn,
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input wire sc,
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input wire di,
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output wire do
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);
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//
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// Variable declaration
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//
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wire debug = 1'b1;
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wire cpol = 1'b0;
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wire cpha = 1'b0;
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reg [7:0] mem [7:0]; // initiate memory
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reg [2:0] mem_adr; // memory address
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reg [7:0] mem_do; // memory data output
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reg [7:0] sri, sro; // 8bit shift register
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reg [2:0] bit_cnt;
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reg ld;
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wire clk;
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//
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// module body
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//
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assign clk = cpol ^ cpha ^ sc;
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// generate shift registers
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always @(posedge clk)
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sri <= #1 {sri[6:0],di};
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always @(posedge clk)
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if (&bit_cnt)
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sro <= #1 mem[mem_adr];
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else
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sro <= #1 {sro[6:0],1'bx};
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assign do = sro[7];
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//generate bit-counter
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always @(posedge clk, posedge csn)
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if(csn)
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bit_cnt <= #1 3'b111;
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else
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bit_cnt <= #1 bit_cnt - 3'h1;
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//generate access done signal
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always @(posedge clk)
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ld <= #1 ~(|bit_cnt);
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always @(negedge clk)
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if (ld) begin
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mem[mem_adr] <= #1 sri;
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mem_adr <= #1 mem_adr + 1'b1;
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end
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initial
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begin
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bit_cnt=3'b111;
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mem_adr = 0;
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sro = mem[mem_adr];
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end
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endmodule
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