mirror of https://github.com/YosysHQ/yosys.git
663 lines
21 KiB
C++
663 lines
21 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <string.h>
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#include <fnmatch.h>
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static std::vector<RTLIL::Selection> work_stack;
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static bool match_ids(RTLIL::IdString id, std::string pattern)
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{
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if (!fnmatch(pattern.c_str(), id.c_str(), FNM_NOESCAPE))
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return true;
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if (id.size() > 0 && id[0] == '\\' && !fnmatch(pattern.c_str(), id.substr(1).c_str(), FNM_NOESCAPE))
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return true;
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return false;
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}
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static bool match_attr_val(const RTLIL::Const &value, std::string pattern)
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{
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if (!fnmatch(pattern.c_str(), value.str.c_str(), FNM_NOESCAPE))
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return true;
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return false;
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}
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static bool match_attr(const std::map<RTLIL::IdString, RTLIL::Const> &attributes, std::string name_pat, std::string value_pat, bool use_value_pat)
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{
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if (name_pat.find('*') != std::string::npos || name_pat.find('?') != std::string::npos || name_pat.find('[') != std::string::npos) {
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for (auto &it : attributes) {
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if (!fnmatch(name_pat.c_str(), it.first.c_str(), FNM_NOESCAPE) && (!use_value_pat || match_attr_val(it.second, value_pat)))
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return true;
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if (it.first.size() > 0 && it.first[0] == '\\' && !fnmatch(name_pat.c_str(), it.first.substr(1).c_str(), FNM_NOESCAPE) && (!use_value_pat || match_attr_val(it.second, value_pat)))
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return true;
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}
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} else {
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if (name_pat.size() > 0 && (name_pat[0] == '\\' || name_pat[0] == '$') && attributes.count(name_pat) && (!use_value_pat || match_attr_val(attributes.at(name_pat), value_pat)))
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return true;
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if (attributes.count("\\" + name_pat) && (!use_value_pat || match_attr_val(attributes.at("\\" + name_pat), value_pat)))
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return true;
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}
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return false;
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}
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static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs)
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{
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if (lhs.full_selection) {
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lhs.full_selection = false;
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lhs.selected_modules.clear();
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lhs.selected_members.clear();
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return;
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}
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if (lhs.selected_modules.size() == 0 && lhs.selected_members.size() == 0) {
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lhs.full_selection = true;
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return;
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}
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RTLIL::Selection new_sel(false);
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for (auto &mod_it : design->modules)
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{
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if (lhs.selected_whole_module(mod_it.first))
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continue;
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if (!lhs.selected_module(mod_it.first)) {
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new_sel.selected_modules.insert(mod_it.first);
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continue;
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}
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RTLIL::Module *mod = mod_it.second;
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for (auto &it : mod->wires)
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if (!lhs.selected_member(mod_it.first, it.first))
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new_sel.selected_members[mod->name].insert(it.first);
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for (auto &it : mod->memories)
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if (!lhs.selected_member(mod_it.first, it.first))
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new_sel.selected_members[mod->name].insert(it.first);
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for (auto &it : mod->cells)
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if (!lhs.selected_member(mod_it.first, it.first))
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new_sel.selected_members[mod->name].insert(it.first);
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for (auto &it : mod->processes)
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if (!lhs.selected_member(mod_it.first, it.first))
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new_sel.selected_members[mod->name].insert(it.first);
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}
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lhs.selected_modules.swap(new_sel.selected_modules);
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lhs.selected_members.swap(new_sel.selected_members);
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}
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static void select_op_union(RTLIL::Design*, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
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{
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if (rhs.full_selection) {
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lhs.full_selection = true;
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lhs.selected_modules.clear();
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lhs.selected_members.clear();
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return;
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}
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if (lhs.full_selection)
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return;
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for (auto &it : rhs.selected_members)
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for (auto &it2 : it.second)
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lhs.selected_members[it.first].insert(it2);
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for (auto &it : rhs.selected_modules) {
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lhs.selected_modules.insert(it);
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lhs.selected_members.erase(it);
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}
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}
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static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
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{
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if (rhs.full_selection) {
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lhs.full_selection = false;
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lhs.selected_modules.clear();
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lhs.selected_members.clear();
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return;
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}
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if (lhs.full_selection) {
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if (!rhs.full_selection && rhs.selected_modules.size() == 0 && rhs.selected_members.size() == 0)
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return;
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lhs.full_selection = false;
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for (auto &it : design->modules)
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lhs.selected_modules.insert(it.first);
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}
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for (auto &it : rhs.selected_modules) {
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lhs.selected_modules.erase(it);
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lhs.selected_members.erase(it);
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}
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for (auto &it : rhs.selected_members)
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{
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if (design->modules.count(it.first) == 0)
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continue;
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RTLIL::Module *mod = design->modules[it.first];
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if (lhs.selected_modules.count(mod->name) > 0)
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{
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for (auto &it : mod->wires)
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lhs.selected_members[mod->name].insert(it.first);
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for (auto &it : mod->memories)
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lhs.selected_members[mod->name].insert(it.first);
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for (auto &it : mod->cells)
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lhs.selected_members[mod->name].insert(it.first);
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for (auto &it : mod->processes)
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lhs.selected_members[mod->name].insert(it.first);
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lhs.selected_modules.erase(mod->name);
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}
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if (lhs.selected_members.count(mod->name) == 0)
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continue;
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for (auto &it2 : it.second)
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lhs.selected_members[mod->name].erase(it2);
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}
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}
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static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
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{
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if (rhs.full_selection)
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return;
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if (lhs.full_selection) {
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lhs.full_selection = false;
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for (auto &it : design->modules)
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lhs.selected_modules.insert(it.first);
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}
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std::vector<RTLIL::IdString> del_list;
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for (auto &it : lhs.selected_modules)
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if (rhs.selected_modules.count(it) == 0) {
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if (rhs.selected_members.count(it) > 0)
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for (auto &it2 : rhs.selected_members.at(it))
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lhs.selected_members[it].insert(it2);
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del_list.push_back(it);
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}
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for (auto &it : del_list)
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lhs.selected_modules.erase(it);
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del_list.clear();
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for (auto &it : lhs.selected_members) {
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if (rhs.selected_modules.count(it.first) > 0)
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continue;
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if (rhs.selected_members.count(it.first) == 0) {
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del_list.push_back(it.first);
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continue;
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}
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std::vector<RTLIL::IdString> del_list2;
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for (auto &it2 : it.second)
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if (rhs.selected_members.at(it.first).count(it2) == 0)
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del_list2.push_back(it2);
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for (auto &it2 : del_list2)
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it.second.erase(it2);
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if (it.second.size() == 0)
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del_list.push_back(it.first);
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}
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for (auto &it : del_list)
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lhs.selected_members.erase(it);
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}
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static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel)
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{
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if (design->selected_active_module.empty())
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return;
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if (sel.full_selection) {
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sel.full_selection = false;
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sel.selected_modules.clear();
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sel.selected_members.clear();
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sel.selected_modules.insert(design->selected_active_module);
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return;
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}
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std::vector<std::string> del_list;
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for (auto mod_name : sel.selected_modules)
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if (mod_name != design->selected_active_module)
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del_list.push_back(mod_name);
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for (auto &it : sel.selected_members)
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if (it.first != design->selected_active_module)
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del_list.push_back(it.first);
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for (auto mod_name : del_list) {
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sel.selected_modules.erase(mod_name);
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sel.selected_members.erase(mod_name);
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}
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}
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static void select_stmt(RTLIL::Design *design, std::string arg)
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{
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std::string arg_mod, arg_memb;
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if (arg.size() == 0)
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return;
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if (arg[0] == '#') {
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if (arg == "#") {
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if (design->selection_stack.size() > 0)
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work_stack.push_back(design->selection_stack.back());
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} else
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if (arg == "#n") {
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if (work_stack.size() < 1)
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log_cmd_error("Must have at least one element on stack for operator #n.\n");
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select_op_neg(design, work_stack[work_stack.size()-1]);
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} else
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if (arg == "#u") {
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if (work_stack.size() < 2)
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log_cmd_error("Must have at least two elements on stack for operator #u.\n");
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select_op_union(design, work_stack[work_stack.size()-2], work_stack[work_stack.size()-1]);
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work_stack.pop_back();
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} else
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if (arg == "#d") {
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if (work_stack.size() < 2)
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log_cmd_error("Must have at least two elements on stack for operator #d.\n");
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select_op_diff(design, work_stack[work_stack.size()-2], work_stack[work_stack.size()-1]);
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work_stack.pop_back();
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} else
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if (arg == "#i") {
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if (work_stack.size() < 2)
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log_cmd_error("Must have at least two elements on stack for operator #i.\n");
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select_op_intersect(design, work_stack[work_stack.size()-2], work_stack[work_stack.size()-1]);
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work_stack.pop_back();
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} else
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log_cmd_error("Unknown selection operator '%s'.\n", arg.c_str());
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select_filter_active_mod(design, work_stack.back());
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return;
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}
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if (arg[0] == '@') {
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std::string set_name = RTLIL::escape_id(arg.substr(1));
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if (design->selection_vars.count(set_name) > 0)
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work_stack.push_back(design->selection_vars[set_name]);
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else
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work_stack.push_back(RTLIL::Selection(false));
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select_filter_active_mod(design, work_stack.back());
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return;
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}
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if (!design->selected_active_module.empty()) {
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arg_mod = design->selected_active_module;
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arg_memb = arg;
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} else {
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size_t pos = arg.find('/');
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if (pos == std::string::npos) {
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arg_mod = arg;
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} else {
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arg_mod = arg.substr(0, pos);
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arg_memb = arg.substr(pos+1);
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}
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}
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work_stack.push_back(RTLIL::Selection());
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RTLIL::Selection &sel = work_stack.back();
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if (arg == "*" && arg_mod == "*") {
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select_filter_active_mod(design, work_stack.back());
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return;
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}
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sel.full_selection = false;
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for (auto &mod_it : design->modules)
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{
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if (!match_ids(mod_it.first, arg_mod))
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continue;
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if (arg_memb == "") {
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sel.selected_modules.insert(mod_it.first);
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continue;
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}
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RTLIL::Module *mod = mod_it.second;
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if (arg_memb.substr(0, 2) == "w:") {
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for (auto &it : mod->wires)
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if (match_ids(it.first, arg_memb.substr(2)))
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sel.selected_members[mod->name].insert(it.first);
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} else
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if (arg_memb.substr(0, 2) == "m:") {
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for (auto &it : mod->memories)
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if (match_ids(it.first, arg_memb.substr(2)))
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sel.selected_members[mod->name].insert(it.first);
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} else
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if (arg_memb.substr(0, 2) == "c:") {
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for (auto &it : mod->cells)
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if (match_ids(it.first, arg_memb.substr(2)))
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sel.selected_members[mod->name].insert(it.first);
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} else
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if (arg_memb.substr(0, 2) == "t:") {
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for (auto &it : mod->cells)
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if (match_ids(it.second->type, arg_memb.substr(2)))
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sel.selected_members[mod->name].insert(it.first);
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} else
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if (arg_memb.substr(0, 2) == "p:") {
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for (auto &it : mod->processes)
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if (match_ids(it.first, arg_memb.substr(2)))
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sel.selected_members[mod->name].insert(it.first);
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} else
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if (arg_memb.substr(0, 2) == "a:") {
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bool use_value_pat = false;
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std::string name_pat = arg_memb.substr(2);
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std::string value_pat;
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if (name_pat.find('=') != std::string::npos) {
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value_pat = name_pat.substr(name_pat.find('=')+1);
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name_pat = name_pat.substr(0, name_pat.find('='));
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use_value_pat = true;
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}
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for (auto &it : mod->wires)
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if (match_attr(it.second->attributes, name_pat, value_pat, use_value_pat))
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sel.selected_members[mod->name].insert(it.first);
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for (auto &it : mod->memories)
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if (match_attr(it.second->attributes, name_pat, value_pat, use_value_pat))
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sel.selected_members[mod->name].insert(it.first);
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for (auto &it : mod->cells)
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if (match_attr(it.second->attributes, name_pat, value_pat, use_value_pat))
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sel.selected_members[mod->name].insert(it.first);
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for (auto &it : mod->processes)
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if (match_attr(it.second->attributes, name_pat, value_pat, use_value_pat))
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sel.selected_members[mod->name].insert(it.first);
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} else {
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if (arg_memb.substr(0, 2) == "n:")
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arg_memb = arg_memb.substr(2);
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for (auto &it : mod->wires)
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if (match_ids(it.first, arg_memb))
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sel.selected_members[mod->name].insert(it.first);
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for (auto &it : mod->memories)
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if (match_ids(it.first, arg_memb))
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sel.selected_members[mod->name].insert(it.first);
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for (auto &it : mod->cells)
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if (match_ids(it.first, arg_memb))
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sel.selected_members[mod->name].insert(it.first);
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for (auto &it : mod->processes)
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if (match_ids(it.first, arg_memb))
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sel.selected_members[mod->name].insert(it.first);
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}
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}
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select_filter_active_mod(design, work_stack.back());
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}
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struct SelectPass : public Pass {
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SelectPass() : Pass("select", "modify and view the list of selected objects") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" select [ -add | -del | -set <name> ] <selection>\n");
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log(" select [ -list | -clear ]\n");
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log(" select -module <modname>\n");
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log("\n");
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log("Most commands use the list of currently selected objects to determine which part\n");
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log("of the design to operate on. This command can be used to modify and view this\n");
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log("list of selected objects.\n");
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log("\n");
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log("Note that many commands support an optional [selection] argument that can be\n");
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log("used to override the global selection for the command. The syntax of this\n");
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log("optional argument is identical to the syntax of the <selection> argument\n");
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log("described here.\n");
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log("\n");
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log(" -add, -del\n");
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log(" add or remove the given objects to the current selection.\n");
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log(" without this options the current selection is replaced.\n");
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log("\n");
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log(" -set <name>\n");
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log(" do not modify the current selection. instead save the new selection\n");
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log(" under the given name (see @<name> below).\n");
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log("\n");
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log(" -list\n");
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log(" list all objects in the current selection\n");
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log("\n");
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log(" -clear\n");
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log(" clear the current selection. this effectively selects the\n");
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log(" whole design.\n");
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log("\n");
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log(" -module <modname>\n");
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log(" limit the current scope to the specified module\n");
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log(" the difference between this and simply selecting the module\n");
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log(" is that all object names are interpreted relative to this\n");
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log(" module after this command until the selection is cleared again.\n");
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log("\n");
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log("When this command is called without an argument, the current selection\n");
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log("is displayed in a compact form (i.e.. only the module name when a whole module\n");
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log("is selected).\n");
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log("\n");
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log("The <selection> argument itself is a series of commands for a simple stack\n");
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log("machine. Each element on the stack represents a set of selected objects.\n");
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log("After this commands have been executed, the union of all remaining sets\n");
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log("on the stack is computed and used as selection for the command.\n");
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log("\n");
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log("Pushing (selecting) object when not in -module mode:\n");
|
|
log("\n");
|
|
log(" <mod_pattern>\n");
|
|
log(" select the specified module(s)\n");
|
|
log("\n");
|
|
log(" <mod_pattern>/<obj_pattern>\n");
|
|
log(" select the specified object(s) from the module(s)\n");
|
|
log("\n");
|
|
log("Pushing (selecting) object when in -module mode:\n");
|
|
log("\n");
|
|
log(" <obj_pattern>\n");
|
|
log(" select the specified object(s) from the current module\n");
|
|
log("\n");
|
|
log("A <mod_pattern> can be a module name or wildcard expression (*, ?, [..])\n");
|
|
log("matching module names.\n");
|
|
log("\n");
|
|
log("An <obj_pattern> can be an object name, wildcard expression, or one of\n");
|
|
log("the following:\n");
|
|
log("\n");
|
|
log(" w:<pattern>\n");
|
|
log(" all wires with a name matching the given wildcard pattern\n");
|
|
log("\n");
|
|
log(" m:<pattern>\n");
|
|
log(" all memories with a name matching the given pattern\n");
|
|
log("\n");
|
|
log(" c:<pattern>\n");
|
|
log(" all cells with a name matching the given pattern\n");
|
|
log("\n");
|
|
log(" t:<pattern>\n");
|
|
log(" all cells with a type matching the given pattern\n");
|
|
log("\n");
|
|
log(" p:<pattern>\n");
|
|
log(" all processes with a name matching the given pattern\n");
|
|
log("\n");
|
|
log(" a:<pattern>\n");
|
|
log(" all objects with an attribute name matching the given pattern\n");
|
|
log("\n");
|
|
log(" a:<pattern>=<pattern>\n");
|
|
log(" all objects with a matching attribute name-value-pair\n");
|
|
log("\n");
|
|
log(" n:<pattern>\n");
|
|
log(" all object with a name matching the given pattern\n");
|
|
log(" (i.e. the n: is optional as it is the default matching rule)\n");
|
|
log("\n");
|
|
log(" @<name>\n");
|
|
log(" push the selection saved prior with 'select -set <name> ...'\n");
|
|
log("\n");
|
|
log("The following actions can be performed on the top sets on the stack:\n");
|
|
log("\n");
|
|
log(" #\n");
|
|
log(" push a copy of the current selection to the stack\n");
|
|
log("\n");
|
|
log(" #n\n");
|
|
log(" replace top set with its invert\n");
|
|
log("\n");
|
|
log(" #u\n");
|
|
log(" replace the two top sets on the stack with their union\n");
|
|
log("\n");
|
|
log(" #i\n");
|
|
log(" replace the two top sets on the stack with their intersection\n");
|
|
log("\n");
|
|
log(" #d\n");
|
|
log(" pop the top set from the stack and subtract it from the new top\n");
|
|
log("\n");
|
|
}
|
|
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
|
|
{
|
|
bool add_mode = false;
|
|
bool del_mode = false;
|
|
bool clear_mode = false;
|
|
bool list_mode = false;
|
|
bool got_module = false;
|
|
std::string set_name;
|
|
|
|
work_stack.clear();
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
std::string arg = args[argidx];
|
|
if (arg == "-add") {
|
|
add_mode = true;
|
|
continue;
|
|
}
|
|
if (arg == "-del") {
|
|
del_mode = true;
|
|
continue;
|
|
}
|
|
if (arg == "-clear") {
|
|
clear_mode = true;
|
|
continue;
|
|
}
|
|
if (arg == "-list") {
|
|
list_mode = true;
|
|
continue;
|
|
}
|
|
if (arg == "-module" && argidx+1 < args.size()) {
|
|
RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
|
|
if (design->modules.count(mod_name) == 0)
|
|
log_cmd_error("No such module: %s\n", mod_name.c_str());
|
|
design->selected_active_module = mod_name;
|
|
got_module = true;
|
|
continue;
|
|
}
|
|
if (arg == "-set" && argidx+1 < args.size()) {
|
|
set_name = RTLIL::escape_id(args[++argidx]);
|
|
continue;
|
|
}
|
|
if (arg.size() > 0 && arg[0] == '-')
|
|
log_cmd_error("Unkown option %s.\n", arg.c_str());
|
|
select_stmt(design, arg);
|
|
}
|
|
|
|
if (clear_mode && args.size() != 2)
|
|
log_cmd_error("Option -clear can not be combined with other options.\n");
|
|
|
|
if (add_mode && del_mode)
|
|
log_cmd_error("Options -add and -del can not be combined.\n");
|
|
|
|
if (list_mode && (add_mode || del_mode))
|
|
log_cmd_error("Option -list can not be combined with -add or -del.\n");
|
|
|
|
if (!set_name.empty() && (list_mode || add_mode || del_mode))
|
|
log_cmd_error("Option -set can not be combined with -list, -add or -del.\n");
|
|
|
|
if (work_stack.size() == 0 && got_module) {
|
|
RTLIL::Selection sel;
|
|
select_filter_active_mod(design, sel);
|
|
work_stack.push_back(sel);
|
|
}
|
|
|
|
while (work_stack.size() > 1) {
|
|
select_op_union(design, work_stack.front(), work_stack.back());
|
|
work_stack.pop_back();
|
|
}
|
|
|
|
assert(design->selection_stack.size() > 0);
|
|
|
|
if (clear_mode)
|
|
{
|
|
design->selection_stack.back() = RTLIL::Selection(true);
|
|
design->selected_active_module = std::string();
|
|
return;
|
|
}
|
|
|
|
if (list_mode)
|
|
{
|
|
RTLIL::Selection *sel = &design->selection_stack.back();
|
|
if (work_stack.size() > 0)
|
|
sel = &work_stack.back();
|
|
sel->optimize(design);
|
|
for (auto mod_it : design->modules)
|
|
{
|
|
if (sel->selected_whole_module(mod_it.first))
|
|
log("%s\n", mod_it.first.c_str());
|
|
if (sel->selected_module(mod_it.first)) {
|
|
for (auto &it : mod_it.second->wires)
|
|
if (sel->selected_member(mod_it.first, it.first))
|
|
log("%s/%s\n", mod_it.first.c_str(), it.first.c_str());
|
|
for (auto &it : mod_it.second->memories)
|
|
if (sel->selected_member(mod_it.first, it.first))
|
|
log("%s/%s\n", mod_it.first.c_str(), it.first.c_str());
|
|
for (auto &it : mod_it.second->cells)
|
|
if (sel->selected_member(mod_it.first, it.first))
|
|
log("%s/%s\n", mod_it.first.c_str(), it.first.c_str());
|
|
for (auto &it : mod_it.second->processes)
|
|
if (sel->selected_member(mod_it.first, it.first))
|
|
log("%s/%s\n", mod_it.first.c_str(), it.first.c_str());
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
if (add_mode)
|
|
{
|
|
if (work_stack.size() == 0)
|
|
log_cmd_error("Nothing to add to selection.\n");
|
|
select_op_union(design, design->selection_stack.back(), work_stack.back());
|
|
design->selection_stack.back().optimize(design);
|
|
return;
|
|
}
|
|
|
|
if (del_mode)
|
|
{
|
|
if (work_stack.size() == 0)
|
|
log_cmd_error("Nothing to delete from selection.\n");
|
|
select_op_diff(design, design->selection_stack.back(), work_stack.back());
|
|
design->selection_stack.back().optimize(design);
|
|
return;
|
|
}
|
|
|
|
if (!set_name.empty())
|
|
{
|
|
if (work_stack.size() == 0)
|
|
design->selection_vars.erase(set_name);
|
|
else
|
|
design->selection_vars[set_name] = work_stack.back();
|
|
return;
|
|
}
|
|
|
|
if (work_stack.size() == 0) {
|
|
RTLIL::Selection &sel = design->selection_stack.back();
|
|
if (sel.full_selection)
|
|
log("*\n");
|
|
for (auto &it : sel.selected_modules)
|
|
log("%s\n", it.c_str());
|
|
for (auto &it : sel.selected_members)
|
|
for (auto &it2 : it.second)
|
|
log("%s/%s\n", it.first.c_str(), it2.c_str());
|
|
return;
|
|
}
|
|
|
|
design->selection_stack.back() = work_stack.back();
|
|
design->selection_stack.back().optimize(design);
|
|
}
|
|
} SelectPass;
|
|
|